3D Chip Package Plank Stack Edge Interposer Alignment
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Solution Overview
Problem
Current chip packaging techniques, such as through-silicon vias (TSVs), are costly and inefficient due to the need for additional processing steps and area consumption, which limits the number of stacked semiconductor dies and complicates thermal management.
Innovation Solution
A chip package design featuring a plank stack of semiconductor dies aligned by positive and negative features, with an interposer plate at a right angle, using conductive materials like solder balls or spring connectors for electrical coupling, eliminating the need for TSVs and allowing for higher density and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to stack memory chips onto a processor, then electrical connection between stacked chips is achieved, but manufacturing cost increases and silicon area is consumed
Solution Approach 1:
The patent segments the interconnection function by separating the TSV formation from the chip stacking process. Instead of forming TSVs through the entire processor chip, the invention uses TSVs only in the memory chips to create bump electrodes, eliminating the need for expensive TSV formation in the processor chip while maintaining electrical connectivity between stacked chips
Solution Approach 2:
The invention extracts the TSV requirement from the processor chip design. By placing TSVs only in the memory chips and using them to form bump electrodes for interconnection, the complex and costly TSV formation process is removed from the processor fabrication, reducing manufacturing cost while preserving the essential electrical connection function
2Reliability
If through-silicon vias (TSVs) are used to stack memory chips, then electrical connection is achieved, but silicon area is consumed reducing transistor density
Solution Approach 1:
The patent segments the TSV placement to memory chips only, allowing the processor chip to maintain full silicon area utilization for transistors and circuits. The TSVs in memory chips serve dual purposes: providing electrical connection and forming bump electrodes for stacking, thus not consuming additional area in the processor
Solution Approach 2:
The TSVs in the memory chips serve multiple functions: they provide electrical connection between layers and simultaneously form the bump electrodes required for stacking. This multi-functionality eliminates the need for separate bump electrode formation structures, reducing overall area consumption in the memory chips while having zero area impact on the processor chip
3Productivity
If face-to-face integration is used to stack memory chips onto a processor, then integration is achieved, but access to power/ground and signal I/O lines is blocked
Solution Approach 1:
The patent transitions from face-to-face integration to edge-to-edge integration, changing the dimensional approach to stacking. By aligning and connecting chips at their edges rather than faces, the configuration allows power/ground and signal I/O lines to remain accessible on the exposed faces of the stacked structure, solving the blocking problem while maintaining integration
4Reliability
If TSVs are used for chip stacking, then electrical connection is achieved, but thermal management becomes more difficult
Solution Approach 1:
The patent segments the thermal management approach by separating the heat dissipation surfaces from the interconnection structures. The edge-to-edge configuration exposes chip faces that can be directly coupled to heat sinks or thermal management structures, providing efficient thermal pathways that are not blocked by the interconnection method itself
Solution Approach 2:
Instead of having the interconnection structures (TSVs) occupy the thermal management surface, the invention inverts the approach by using edge connections that leave the chip faces fully exposed for thermal management. This inversion allows thermal management structures to be applied directly to the largest available surfaces rather than being constrained by through-chip interconnections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables low-cost, low-latency, and high-performance 3D stacks of semiconductor dies with reduced latency and power consumption, accommodating a larger number of dies and improving thermal management by avoiding the overhead of TSVs.
Implementation Method 1
The chip package includes an interposer plate electrically coupled to the semiconductor dies along the x direction... This electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.
Data Source
AI summary
In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.