Plasma Circuit Delayering for Uniform Whole-Die Etching
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Solution Overview
Problem
Conventional delayering methods for semiconductor dies are limited by small delayering areas, time-consuming stitching of field of views, and difficulties in handling larger dies due to ion beam constraints and non-uniform material removal, especially as device nodes shrink and layers increase.
Innovation Solution
Employing plasma-based etching processes, such as Reactive Ion Etch (RIE) and Inductively Coupled Plasma (ICP), to uniformly delayer entire semiconductor dies or wafers, using controlled ion currents and free radical densities for uniform layer removal across larger areas, overcoming limitations of conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional FIB-based delayering methods are used, then uniform material removal can be achieved, but the delayering area is constrained to small regions (tens of square microns)
Solution Approach 1:
The patent replaces the mechanical ion beam-based FIB system with a plasma-based chemical etching system. This substitution allows the process to operate on a much larger scale (entire die or wafer level) while maintaining uniform material removal through controlled plasma chemistry rather than localized ion beam bombardment.
Solution Approach 2:
The patent changes the fundamental parameters of the delayering process by using plasma chemistry (reactive species, temperature, pressure) instead of ion beam parameters (current density, beam focus). This enables uniform etching across large areas by controlling plasma distribution and chemistry rather than mechanical beam scanning.
2Area of stationary object
If FIB delayering is performed on large areas, then the delayering area increases, but the process becomes time-consuming due to sequential field stitching
Solution Approach 1:
The patent merges multiple small-field delayering operations into a single unified plasma etching process that treats the entire die or wafer simultaneously. This eliminates the need for sequential stitching of multiple fields, dramatically reducing processing time while maintaining large area coverage.
Solution Approach 2:
The plasma-based process enables continuous uniform etching across the entire surface without interruption for repositioning or stitching operations. The plasma field continuously acts on all exposed surfaces simultaneously, maintaining constant material removal rate across the full processing area.
3Quantity of substance
If device nodes are shrunk and metal layers are increased, then device density and performance improve, but delayering complexity and time increase
Solution Approach 1:
The patent replaces the complex, layer-by-layer mechanical FIB delayering process with a unified plasma etching approach that can handle multiple layers simultaneously. The chemical etching process naturally progresses through stacked layers without requiring separate operations for each layer, reducing complexity despite increased device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables uniform and efficient delayering of entire semiconductor dies or wafers without the need for stitching, improving analysis efficiency and reducing processing time by maintaining uniformity and flexibility in material removal.
Implementation Method 1
exposing a semiconductor die to plasma of an etching gas
Implementation Method 2
an anisotropic plasma-based reactive ion etch (RIE) to remove the dielectric films
Implementation Method 3
the layers are removed using the FIB with gas-assist chemistry
Implementation Method 4
The gas-assist methods enable controlled delayering, in which metal features as well as insulating films are removed at comparable rates
Data Source
AI summary
The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.


