Plasma-Induced Damage Checks for Circuit Design Verification
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Solution Overview
Problem
Current methods for verifying circuit designs against plasma-induced damage (PID) are inefficient, particularly in detecting risk connections versus protection connections during plasma etching, leading to potential charging damage in MOSFETs.
Innovation Solution
A method that identifies the lowest risk protection layer by analyzing metal layers for risk and protection connections, determining if connections are established at this layer, and returning a PASS or FAIL result based on complete protection, thereby optimizing the analysis to eliminate unnecessary checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current methods are used to verify circuit designs against plasma-induced damage, then verification can be performed, but the runtime is excessive and efficiency is low
Solution Approach 1:
The method performs preliminary action by first identifying the lowest risk protection layer before conducting full verification. It pre-determines which metal layers need to be analyzed by finding the lowest layer where risk connections are established, thereby avoiding unnecessary analysis of higher layers and reducing overall runtime.
Solution Approach 2:
The verification process is segmented into distinct phases: first identifying risk connections and their lowest layers, then determining protection connections at those specific layers. This segmentation allows the system to focus only on critical layers rather than analyzing all metal layers uniformly, improving efficiency.
2Reliability
If all metal layers are analyzed for risk and protection connections, then complete verification is achieved, but redundant analyses increase runtime
Solution Approach 1:
The system performs preliminary identification of the lowest risk protection layer before conducting full verification. By pre-determining which metal layers contain risk connections and finding the lowest such layer, the system can then focus verification only on those critical layers, avoiding redundant analysis of higher layers while maintaining completeness.
Solution Approach 2:
The method extracts only the essential information needed for verification - specifically, the lowest layer where risk connections are established. By taking out and focusing only on this critical layer for protection connection analysis, the system eliminates redundant analysis of higher layers while preserving verification completeness.
Data Source
AI summary
Methods for circuit design verification and corresponding systems and computer-readable mediums. A method includes receiving a plasma induced damage (PID) group defining a plurality of metal layers and having at least one risk connection comprising a plurality of risk links, and at least one corresponding protection connection comprising a plurality of protection links. The method includes identifying a lowest risk protection layer as a lowest of plurality of metal layers at which any of the risk links is established. The method includes determining whether a connection is established for all of the protection links at the lowest risk protection layer. The method includes, when it is determined that a connection is established for all of the protection links at the lowest risk protection layer, then returning a PASS result.