Plasma Fin Etching with Passivation for Dense-Isolated Trench Control
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in reducing minimum feature sizes while preventing leakage current and damage to epitaxial source/drain regions, and achieving adequate depth and small lateral width in insulation structures.
Innovation Solution
The implementation of a Continuous Poly On Diffusion Edge (CPODE) structure and plasma etching processes to pattern transistors, which involves forming a CPODE structure that divides fins, using passivation-oriented and etchant-oriented etching to achieve deep vertical depth and small lateral width, and controlling etch rates to avoid leakage and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage current and damage to epitaxial source/drain regions occur
Solution Approach 1:
A passivation layer is formed on the sidewalls of trenches before the etching process completes, creating a protective barrier in advance. This preliminary action prevents leakage current and damage to epitaxial source/drain regions by establishing protection before the harmful effects can occur during miniaturization processing.
Solution Approach 2:
The passivation layer acts as an intermediary between the etching process and the epitaxial source/drain regions. It mediates the interaction by absorbing or blocking harmful effects from the etchant, allowing the etching to proceed while protecting the sensitive regions from damage and leakage current.
2Length of stationary object
If etching depth is increased to achieve deeper vertical trenches, then adequate depth for insulation structures is achieved, but lateral width control becomes difficult and damage to surrounding regions increases
Solution Approach 1:
The passivation layer is selectively formed only on the sidewalls of the trenches, providing localized protection where needed. This local quality approach allows deep vertical etching while maintaining lateral width control in the bulk material, as the protection is applied precisely where the epitaxial regions are vulnerable without affecting the overall etching geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates leakage current and damage to epitaxial source/drain regions, enabling deeper vertical etches in dense regions and shallower etches in isolated regions, thus enhancing the integration density and reliability of semiconductor devices.
Implementation Method 1
performing a plasma etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region
Implementation Method 2
The plasma etch process includes performing a passivation-oriented process and an etchant-oriented process
Data Source
AI summary
Methods for fabricating semiconductor devices are provided. An exemplary method includes forming fins in a dense region and in an isolated region of a semiconductor substrate; performing a plasma dry etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region, wherein the plasma dry etch process includes: performing a passivation-oriented process and an etchant-oriented process; and controlling the passivation-oriented process and the etchant-oriented process to form the first trench with a desired first critical dimension and first depth and to form the second trench with a desired second critical dimension and second depth.