Plasma Oxidation for Memory Transistor Blocking Structures
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Solution Overview
Problem
Conventional oxide formation methods for dielectric layers in semiconductor structures require high thermal budgets, leading to structural deformation and dopant diffusion, which affects the accuracy and reliability of the semiconductor devices.
Innovation Solution
A high density plasma oxidation process is used to form dielectric layers at lower temperatures, reducing thermal stress and allowing for precise control of layer thickness, resulting in more uniform and reliable semiconductor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxidation methods (CVD, ISSG, HTO) are used to form dielectric layers, then oxide deposition is achieved, but the process temperature exceeds 900°C causing structural deformation and dopant diffusion
Solution Approach 1:
The patent changes the fundamental parameter of oxidation temperature from conventional high temperatures (>900°C) to low temperature (below 900°C) by switching from thermal oxidation methods to plasma-based oxidation. This parameter change enables oxide formation while preserving structural integrity and preventing dopant diffusion.
Solution Approach 2:
The patent replaces thermal field-based oxidation (heat-driven chemical vapor deposition and thermal oxidation) with plasma field-based oxidation. The plasma process uses ionized gas species and reactive oxygen radicals to achieve oxidation at lower temperatures, substituting thermal energy with plasma energy.
2Manufacturing precision
If high temperature oxidation processes are used, then dielectric layers are formed, but dopant diffusion occurs causing shifts in device electrical parameters
Solution Approach 1:
The patent changes the temperature parameter to below 900°C during oxidation, which is sufficient to form the dielectric layer but low enough to prevent dopant diffusion. This precise temperature control maintains electrical parameter accuracy while achieving complete oxidation.
Solution Approach 2:
The patent substitutes thermal oxidation with plasma oxidation, where ionized oxygen species and reactive radicals provide the oxidation mechanism without requiring high thermal energy. This substitution eliminates the temperature-induced dopant diffusion problem while maintaining oxidation effectiveness.
3Reliability
If conventional CVD oxidation is used, then dielectric layers are deposited, but high thermal budget causes structural deformation
Solution Approach 1:
The patent replaces thermal field-based energy input with plasma field-based energy input. The plasma process uses electromagnetic energy to generate ionized species that chemically react with the substrate at lower temperatures, substituting high thermal budget with lower thermal plus plasma energy input.
Solution Approach 2:
The patent changes the energy input parameters from high temperature thermal energy to lower temperature plasma energy. This parameter change reduces the thermal budget from >900°C to <900°C, preventing structural deformation while achieving complete oxidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high density plasma oxidation process enables the formation of semiconductor structures with improved accuracy and reliability by maintaining structural integrity and preventing dopant diffusion, while reducing manufacturing costs through lower thermal budgets.
Implementation Method 1
forming a blocking structure on the charge storage layer by plasma oxidation
Implementation Method 2
high density plasma oxidation process
Data Source
AI summary
A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.