Plasma Roughened Passivation for Wafer Adhesion

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Solution Overview

Problem

In semiconductor packaging, the adhesion of chips to a reconstituted wafer is often inadequate, leading to 'flying dies' due to various stresses and forces during the packaging process, which reduces the yield of viable packages and increases manufacturing costs.

Innovation Solution

Exposing the passivation layer of the semiconductor wafer to ionized gas to roughen its surface, allowing for improved adhesion of chips to an adhesion layer and subsequent encapsulation, which enhances the stability of the chips during the packaging process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If adhesive glue, adhesive tape, or epoxy resin is used to affix chips to a reconstituted wafer, then the chips can be attached to the wafer surface, but the chips may move or become dislodged due to stresses and forces during the packaging process

Engineering Contradiction:
Improveadhesion strengthVSAvoidchip stability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The passivation layer surface is roughened in advance before the chips are affixed to the reconstituted wafer. This preliminary surface treatment creates a roughened topology that enhances adhesion when the chips are subsequently attached, preventing them from moving or becoming dislodged during packaging processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The surface parameters of the passivation layer are changed by exposing it to ionized gas, which transforms the smooth surface into a roughened surface. This parameter change in surface topology increases the contact area and mechanical interlocking capability, thereby improving adhesion strength without requiring additional adhesives.

Inventive Principle:
Principle #35Parameter changes

2Strength

If the passivation layer surface is smooth, then the manufacturing process is simple, but the adhesion of chips to the adhesion layer is inadequate

Engineering Contradiction:
Improveadhesion strengthVSAvoidprocess complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The mechanical process of surface roughening is replaced by exposing the passivation layer to ionized gas. This substitution uses plasma chemistry to achieve surface modification without mechanical contact, maintaining process simplicity while effectively increasing adhesion strength through surface roughening.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If chips are tightly adhered to prevent movement, then flying dies are reduced, but the manufacturing cost increases due to reduced yield and additional process steps

Engineering Contradiction:
Improvechip adhesion reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The passivation layer itself provides the adhesion function through its roughened surface topology. By exposing the passivation layer to ionized gas, the surface automatically gains enhanced adhesion properties without requiring additional adhesive materials or complex processing steps, thereby reducing manufacturing costs while improving chip adhesion reliability.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The roughened surface of the passivation layer increases the contact area and adhesion strength, reducing the likelihood of chips becoming dislodged during encapsulation and improving the overall throughput and reliability of semiconductor packages.

Implementation Method 1

The passivation layer is exposed to ionized gas, which causes a surface of the passivation layer to roughen

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS8912653B2Plasma treatment on semiconductor wafers
Publication Date: 2014.12.16 STMICROELECTRONICS INT NV
  • US8912653B2 patent drawing
  • US8912653B2 patent drawing
  • US8912653B2 patent drawing

AI summary

A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.