Plasma Sheath Modifier for Lithography Roughness Control
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Solution Overview
Problem
Optical lithography processes face challenges with line width roughness (LWR) and line edge roughness (LER) in forming features below 100 nm, leading to non-uniform circuits and device degradation, as existing methods either introduce defects or alter the resist pattern, and ion implantation can cause faceting in silicon fins.
Innovation Solution
A method involving a plasma sheath modifier to generate a plasma sheath with ions incident over a wide angular range, which treats patterned resist features and permanent substrate features, reducing LWR and LER through plasma immersion ion implantation and doping, while maintaining control over critical dimensions and resist attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional optical lithography is used to pattern substrates, then high throughput is achieved, but line width roughness and line edge roughness increase leading to non-uniform circuits
Solution Approach 1:
The patent applies preliminary ion implantation to the photoresist pattern before the etching process. This preliminary action modifies the photoresist properties in advance, making it more resistant to etching and reducing the transfer of roughness features to the final circuit pattern, thereby maintaining manufacturing precision while preserving high throughput
2Manufacturing precision
If ion implantation is used to treat patterned features, then line width roughness and line edge roughness are reduced, but faceting occurs in silicon fins
Solution Approach 1:
The patent employs selective ion implantation by positioning the ion source at a specific distance and angle from the substrate, creating a non-uniform ion flux distribution. This local quality approach allows the ion implantation to effectively reduce roughness on horizontal surfaces while minimizing the harmful faceting effect on vertical silicon fin surfaces
Solution Approach 2:
The patent carefully controls ion implantation parameters including ion energy (50-200 eV), ion flux density, and exposure time to achieve the desired reduction in line width roughness and line edge roughness while preventing excessive faceting in silicon fins
3Manufacturing precision
If existing methods are used to reduce line width roughness, then some roughness improvement is achieved, but defects are introduced or resist pattern is altered
Solution Approach 1:
The patent replaces chemical etching methods with physical ion implantation to reduce line width roughness. This substitution avoids the introduction of chemical defects and unwanted alterations to the resist pattern that occur with chemical-based approaches, maintaining pattern integrity while improving manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces LWR and LER by 40% with minimal critical dimension shrinkage and faceting, enabling the formation of high-quality patterns and devices with improved performance by isotropically hardening resist features and maintaining resist profile integrity.
Implementation Method 1
A method is provided for implanting ions into a substrate. The method includes generating a plasma in a process chamber and positioning a plasma sheath modifier adjacent to the process chamber. The plasma sheath modifier generates a plasma sheath with ions incident over a wide angular range. The plasma sheath is positioned over a set of patterned resist features on a first side of the substrate and over a set of permanent substrate features on a second side of the substrate. The patterned resist features and the permanent substrate features are exposed to the plasma sheath for a selected period of time.
Implementation Method 2
This approach effectively reduces LWR and LER by 40% with minimal critical dimension shrinkage and faceting, enabling the formation of high-quality patterns and devices with improved performance by isotropically hardening resist features and maintaining resist profile integrity.
Data Source
AI summary
A method of treating resist features comprises positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and generating a plasma in the process chamber having a plasma sheath adjacent to the first side of the substrate. The method may further comprise modifying a shape of a boundary between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the shape of the boundary is not parallel to a plane defined by a front surface of the substrate facing the plasma, wherein ions from the plasma impinge on the patterned resist features over a wide angular range during a first exposure.