Plate Capacitor Support-Layer Layout for High-Density DRAM

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Solution Overview

Problem

The challenge of manufacturing semiconductor structures, particularly DRAM capacitors, lies in the high aspect ratio and shrinking size, which complicates capacitor fabrication and leads to issues like delamination and uneven filling.

Innovation Solution

A method involving the formation of support layers on a base, followed by a bottom electrode layer and a dielectric layer, transforming columnar capacitors into plate capacitors, and utilizing a mask layer to etch trenches, resulting in independent, hexagonal or tetragonal packed capacitor structures to improve space utilization and prevent delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the integration level increases and capacitor size shrinks, then storage density is improved, but the aspect ratio of the capacitor becomes increasingly high leading to manufacturing challenges

Engineering Contradiction:
Improvestorage densityVSAvoidcapacitor fabrication
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The capacitor structure is divided into multiple support layers (first support layer, second support layer, etc.) stacked vertically. Each support layer provides structural support independently, allowing the overall capacitor to achieve high aspect ratio without compromising structural integrity during manufacturing. This segmentation enables high storage density while maintaining manufacturability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar capacitor structures to three-dimensional stacked structures with support layers extending in the vertical dimension. The support layers are arranged at intervals along the vertical direction, creating a multi-layered architecture that increases storage density without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional capacitor manufacturing methods are used, then manufacturing process is simple, but delamination and uneven filling occur

Engineering Contradiction:
Improvemanufacturing processVSAvoiddelamination and uneven filling
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Support layers are formed in advance before the dielectric layer and electrode layers are deposited. These pre-formed support layers provide a scaffold that guides subsequent material deposition, ensuring uniform filling and preventing delamination issues that would otherwise occur in high aspect ratio structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The support layers act as intermediary structures between the base substrate and the dielectric/electrode layers. They provide mechanical support and structural guidance during the manufacturing process, mediating between the substrate and the capacitor components to prevent manufacturing defects.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If columnar capacitors are used, then manufacturing is straightforward, but space utilization is low

Engineering Contradiction:
Improvemanufacturing straightforwardnessVSAvoidspace utilization
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent employs support layers that extend in the vertical direction rather than only in the planar direction. This three-dimensional arrangement allows capacitor structures to utilize vertical space effectively, increasing storage density without requiring larger planar area, thus improving space utilization while maintaining manufacturing feasibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12557304B2Method of manufacturing semiconductor structure and semiconductor structure
Publication Date: 2026.02.17 CHANGXIN MEMORY TECH INC
  • US12557304B2 patent drawing
  • US12557304B2 patent drawing
  • US12557304B2 patent drawing

AI summary

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base; forming a plurality of support layers on the base, where the support layers are configured to support a plate capacitor structure, extend along a first direction, and are arranged at intervals along a second direction, and the first direction intersects the second direction; forming a bottom electrode layer, where the bottom electrode layer at least covers sidewalls of the support layers; and forming a dielectric layer, the dielectric layer covering the bottom electrode layer.