Plateau-Shaped Overlay Mark for Semiconductor Alignment
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving proper alignment of layered structures due to poor image quality of overlay marks, which can result in device failure or low performance, especially as semiconductors shrink in size and require higher image quality.
Innovation Solution
A method involving the formation of a plateau-shaped overlay mark and active fins, using a hard mask layer and silicon patterns, followed by anisotropic etching and organic planarizing layers to create reliable mask patterns for precise alignment during photolithography, ensuring high-contrast detection and accurate pattern transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional overlay mark is used, then the fabrication process is simple, but the image quality of the overlay mark is poor resulting in misalignment
Solution Approach 1:
The overlay mark is segmented into multiple components: a plateau-shaped main body and multiple fin structures positioned at specific locations. This segmentation allows each component to serve a specific function - the plateau provides a stable reference plane while the fins enhance contrast and facilitate precise alignment detection, thereby improving image quality without excessive complexity
Solution Approach 2:
Different regions of the overlay mark structure are given different properties: the plateau region provides a flat reference surface while the fin regions provide high-contrast edges. This local differentiation of structural qualities enables the overlay mark to simultaneously provide both a stable reference plane and high-contrast alignment features, resolving the contradiction between simplicity and image quality
2Length of moving object
If the semiconductor device size is reduced, then the device scaling is achieved, but the requirements for overlay mark image quality become more stringent
Solution Approach 1:
The overlay mark design transitions from a two-dimensional planar pattern to a three-dimensional structure with a plateau and vertically extending fins. This dimensional enhancement provides additional contrast mechanisms and reference features that remain effective even as device dimensions shrink, allowing precise alignment to be maintained at smaller scales
3Manufacturing precision
If a plateau-shaped overlay mark with fins is formed, then the alignment precision is improved, but the number of process steps increases
Solution Approach 1:
The formation of the overlay mark structure is merged with the existing hard mask patterning process. The same hard mask layer and etching steps that define the device patterns are also used to create the plateau and fin structures of the overlay mark, thereby achieving enhanced alignment precision without adding significant process complexity
Solution Approach 2:
The hard mask layer serves multiple functions: it defines the device patterns, creates the plateau structure, and forms the fin structures of the overlay mark. This multi-functionality allows the overlay mark to be created as an integrated part of the standard fabrication process, reducing the number of additional steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of overlay marks, improving the alignment of subsequent patterns and reducing the risk of device failure by providing a clear, high-contrast reference for photolithography, thus ensuring better performance and precision in semiconductor device fabrication.
Implementation Method 1
an anisotropic etching process is performed on the oxide layer to form a plurality of line-shaped oxide patterns and a first ring-shaped oxide pattern, a second ring-shaped oxide pattern and a third ring-shaped oxide pattern
Data Source
AI summary
The disclosure relates to methods of fabricating semiconductor devices. A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.