Plated Conductive Layer for Semiconductor Package Thickness Reduction
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Solution Overview
Problem
Conventional semiconductor packages, such as QFN packages, are limited in thickness by the thickness of the lead frame, which restricts the overall package thinness and can lead to issues like die pad delamination and heat dissipation challenges.
Innovation Solution
The semiconductor die is positioned on a thin plated conductive layer, with wire bonds to leads that are recessed with respect to an encapsulation material, allowing the package to be thinner and improving heat dissipation by using a conductive layer that replaces the traditional lead frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional lead frame is used to support the semiconductor die and leads, then the package has sufficient mechanical strength and structural stability, but the package thickness is increased and weight is added
Solution Approach 1:
The patent extracts and removes the conventional lead frame structure from the package, retaining only the essential functional elements (die pad and leads) formed as thin plated conductive layers directly on the substrate. This eliminates the thick lead frame while maintaining the necessary mechanical support through alternative means (substrate and encapsulant).
Solution Approach 2:
The patent employs thin plated conductive layers (die pad and leads) formed by electroplating or electroless plating processes, replacing the rigid thick lead frame with thin film structures. These thin films provide the necessary electrical and mechanical functions while minimizing thickness contribution to the overall package.
2Temperature
If a conventional lead frame is used, then the die pad and leads are mechanically supported, but heat dissipation is impaired and delamination risks increase
Solution Approach 1:
The patent changes the physical and thermal parameters of the package structure by replacing the lead frame with thin plated conductive layers having different thermal conductivity and expansion characteristics. This parameter change improves heat dissipation pathways while reducing thermal stress and delamination risks through better thermal management and matched expansion properties.
Solution Approach 2:
The patent creates a composite structure where the substrate, thin plated conductive layers, and encapsulant work together as an integrated system. This composite approach combines materials with complementary properties to achieve both mechanical support and improved thermal performance, while the integrated structure eliminates interfaces that could lead to delamination.
3Length of moving object
If wire bonds are made to lead frame leads, then electrical connections are established, but the loop height is increased
Solution Approach 1:
The patent creates a simplified geometric copy or representation of the traditional lead frame lead structure through the thin plated conductive layer leads. These leads are formed with precise patterns and positions that replicate the necessary electrical connection points but with reduced dimensions, thereby reducing wire bond loop heights while maintaining functional equivalence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thinner semiconductor package with reduced loop height of conductive wires, improved heat dissipation, and reduced delamination risks due to the compliance of the plated conductive layer, addressing the limitations of conventional packages.
Implementation Method 1
improved heat dissipation by using a conductive layer that replaces the traditional lead frame
Implementation Method 2
a plated conductive layer in a first cavity of a substrate... wire bonds between the active surface of the semiconductor die and the plated conductive layers
Data Source
AI summary
In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.