Plated Wall WCSP Cavities Without Thermal Die Damage
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Solution Overview
Problem
Subtractive processes used to form cavities in semiconductor packages cause thermal damage to the semiconductor die and conductive terminals, affecting operational and mechanical integrity and lifespan.
Innovation Solution
A semiconductor package with a mold compound cavity defined by vertical plated walls that prevent mold compound from flowing into the cavity during injection, using a non-subtractive process to mitigate thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If subtractive processes are used to form cavities in semiconductor packages, then cavities can be formed to accommodate additional components, but thermal damage occurs to the semiconductor die and conductive terminals
Solution Approach 1:
Instead of removing material to form a cavity (subtractive process), the patent uses a additive approach by forming plated walls that define the cavity space during mold compound injection. The cavity is created by the presence of walls rather than by removal of material, completely avoiding thermal damage from laser ablation or mechanical drilling.
Solution Approach 2:
The plated walls act as intermediary structures that define the cavity boundary and prevent mold compound from flowing into the cavity during injection. These walls are formed through electroplating on a seed layer, creating a protective barrier that shapes the cavity without direct thermal contact to the semiconductor die or conductive terminals.
2Object-affected harmful factors
If plated walls are formed using electroplating, then a non-subtractive cavity formation process is achieved, but additional manufacturing steps are required
Solution Approach 1:
The patent combines multiple functions into the plated wall structure: it serves as a seed layer substrate, a structural barrier to define the cavity, and a mold release surface. The electroplating process is integrated into the existing semiconductor packaging flow, where the plated walls are formed on the mold cavity insert before die attachment, consolidating the cavity formation process into the mold preparation stage rather than requiring separate post-processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively forms a mold compound cavity without thermal damage, enhancing the operational and mechanical integrity of the semiconductor package and allowing efficient use of space for additional components.
Implementation Method 1
one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space
Implementation Method 2
performing a second photolithographic process to electroplate one or more walls circumscribing the conductive terminal
Data Source
AI summary
In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.