Platform Clock Control for Wireless Interference Mitigation

Solution Overview

Problem

The increasing internal interference within processing platforms due to electromagnetic radiation from platform devices operating at or near carrier frequencies degrades wireless communication performance, and existing solutions like Dynamic Voltage Frequency Scaling (DVFS) negatively impact system performance and power consumption.

Innovation Solution

Implementing interference logic circuitry that signals protect and unprotect requests to the platform controller based on internal interference thresholds, allowing optimized clock frequency adjustments during power save modes and reducing interference on wireless communication channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DVFS is used to reduce internal interference, then wireless communication performance is improved, but system performance and power consumption are negatively impacted

Engineering Contradiction:

Improvewireless communication performanceVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic clock frequency adjustment for platform devices based on real-time interference detection and power save mode status. The platform controller dynamically scales clock frequencies up or down depending on whether the wireless device is in active mode or power save mode, and whether interference thresholds are exceeded. This dynamic approach maintains system performance during active operation while reducing interference during power save modes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter of platform devices conditionally based on interference levels and power save mode status. Instead of using DVFS which continuously adjusts voltage and frequency, this patent selectively adjusts clock frequencies only when interference is detected and the wireless device is in power save mode, thereby maintaining system performance during normal operation while mitigating interference when necessary.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If DVFS is used to reduce internal interference, then wireless communication performance is improved, but power consumption is negatively impacted

Engineering Contradiction:

Improvewireless communication performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic clock frequency adjustment for platform devices based on real-time interference detection and power save mode status. The platform controller dynamically scales clock frequencies up or down depending on whether the wireless device is in active mode or power save mode, and whether interference thresholds are exceeded. This dynamic approach maintains system performance during active operation while reducing interference during power save modes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter of platform devices conditionally based on interference levels and power save mode status. Instead of using DVFS which continuously adjusts voltage and frequency, this patent selectively adjusts clock frequencies only when interference is detected and the wireless device is in power save mode, thereby maintaining system performance during normal operation while mitigating interference when necessary.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If clock frequencies are adjusted to reduce interference, then wireless communication reliability is improved, but system performance is degraded

Engineering Contradiction:

Improvewireless communication reliabilityVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic clock frequency adjustment for platform devices based on real-time interference detection and power save mode status. The platform controller dynamically scales clock frequencies up or down depending on whether the wireless device is in active mode or power save mode, and whether interference thresholds are exceeded. This dynamic approach maintains system performance during active operation while reducing interference during power save modes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter of platform devices conditionally based on interference levels and power save mode status. Instead of using DVFS which continuously adjusts voltage and frequency, this patent selectively adjusts clock frequencies only when interference is detected and the wireless device is in power save mode, thereby maintaining system performance during normal operation while mitigating interference when necessary.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260005715A1Methods and arrangements to manage platform interference

Publication Date: 2026.01.01 INTEL CORP

AI summary

Logic to communicate an unprotect signal to a platform controller, the unprotect signal to indicate a first time frame during which protection of wireless communications from internal interference received at an antenna is not requested. The internal interference to comprise electromagnetic radiation emanating from a platform device based on operations by the platform device at a clock frequency. The protection to involve adjustment, by the platform controller of a clock frequency for the operations.