Plating Bump Sagging Prevention in Printed Wiring Boards
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Solution Overview
Problem
Conventional printed wiring boards with multiple plating bumps face issues with the top plating layer sagging onto the side surfaces of the intermediate and base plating layers during reflow, leading to unreliable connections due to inadequate thickness of the intermediate layer.
Innovation Solution
A printed wiring board design featuring a base insulating layer, a conductor layer with pads, a solder resist layer with openings, and plating bumps composed of a base plating layer, an intermediate layer with a thickness of 2.7-7.0 μm, and a top plating layer that is reflowed into a hemispherical shape covering only the upper surface of the intermediate layer, preventing sagging by maintaining the bump at a predetermined height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top plating layer is made thick to ensure reliable connection, then connection reliability is improved, but the top plating layer sags onto the side surfaces during reflow, causing manufacturing defects
Solution Approach 1:
The invention changes the thickness parameter of the intermediate layer to a specific range (2.7-7.0 μm) to control the reflow behavior of the top plating layer. This parameter adjustment prevents sagging while maintaining connection reliability, resolving the contradiction between reliable connection and shape control.
Solution Approach 2:
The intermediate layer acts as a mediator between the base plating layer and the top plating layer. By controlling its thickness within 2.7-7.0 μm, it provides support to prevent the top plating layer from sagging during reflow, while still allowing adequate connection reliability through the layered structure.
2Device complexity
If the intermediate layer is made thin to reduce complexity, then device complexity is reduced, but the top plating layer sags during reflow, worsening manufacturing precision
Solution Approach 1:
The invention identifies a critical thickness range (2.7-7.0 μm) for the intermediate layer that balances structural simplicity with functional performance. This specific parameter range prevents sagging without requiring excessive layer complexity, resolving the contradiction between device complexity and manufacturing precision.
3Device complexity
If the top plating layer is allowed to sag to simplify the structure, then device complexity is reduced, but connection reliability deteriorates due to inadequate thickness distribution
Solution Approach 1:
The intermediate layer with controlled thickness (2.7-7.0 μm) serves as a mediator that maintains the structural integrity of the plating bump. It prevents sagging-induced reliability issues while keeping the overall structure relatively simple, resolving the contradiction between device complexity and connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The specified thickness of the intermediate layer and the hemispherical shape of the top plating layer ensure stable and reliable connections by preventing sagging, enhancing the connection reliability between the plating bumps and electronic components.
Implementation Method 1
reflowing the top plating layer such that the top plating layer has a hemispherical shape
Data Source
AI summary
A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including pads, a solder resist layer formed on the base layer such that the solder resist layer is covering the conductor layer and has openings exposing the pads, and plating bumps formed on the pads such that each plating bump includes a base plating layer formed in a respective one of the openings, an intermediate layer formed on the base plating layer, and a top plating layer formed on the intermediate layer. The plating bumps are formed such that the base plating layer has a side surface including a portion protruding from the solder resist layer, that the intermediate layer has a thickness in a range of 2.7 to 7.0 μm, and that the top plating layer has a hemispherical shape and is covering only an upper surface of the intermediate layer.