Plating Stub Capacitance for High-Frequency Signal Reflections

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Solution Overview

Problem

High-frequency chip packages experience signal performance degradation due to reflections from open plating stubs, particularly causing detrimental quarter-wave length resonance during high-speed data transmissions.

Innovation Solution

Capacitively coupling the plating stubs to ground using either a discrete capacitor or an embedded capacitor structure within the multi-layered package substrate shifts the resonant frequency away from operational frequencies, minimizing signal reflections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electroplating is used to apply precious metals to signal interconnects, then electrical conductivity and material properties are improved, but open plating stubs are created that cause signal reflections and resonance at high frequencies

Engineering Contradiction:
Improveelectrical conductivityVSAvoidsignal reflections from plating stubs
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The harmful plating stub is extracted and isolated from the signal path by creating a separate capacitive coupling path to ground. The capacitor connects the plating stub to ground, extracting the harmful resonant effect from the signal transmission path while preserving the beneficial conductive properties of the plated interconnect.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

A capacitor is introduced as an intermediary element between the plating stub and ground. This intermediary component provides a controlled impedance path that prevents the plating stub from causing signal reflections and resonance, while allowing the plating to maintain its electrical conductivity function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If plating stubs are left intact after electroplating, then manufacturing simplicity is maintained, but signal performance deteriorates due to reflections and quarter-wave resonance

Engineering Contradiction:
Improveelectroplating process simplicityVSAvoidsignal transmission quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The capacitive coupling structure is designed and positioned in advance during the PCB manufacturing process, before signal transmission occurs. This preliminary arrangement ensures that the plating stubs are pre-configured with their capacitive load, preventing resonance issues before they affect signal quality, while maintaining manufacturing simplicity.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If conventional electroplating processes are used, then material application is straightforward and cost-effective, but detrimental resonance effects occur at high operational frequencies

Engineering Contradiction:
Improveelectroplating processVSAvoidquarter-wave resonance
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The electrical parameters of the plating stub are changed by introducing capacitive coupling to ground. This parameter modification shifts the resonant frequency of the plating stub away from the operational signal frequencies, eliminating the quarter-wave resonance effect while maintaining the straightforward electroplating process for material application.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces signal interference by shifting the resonant frequency below operational frequencies, improving signal transmission quality by approximately 15 dB as shown in the graph, and is more economical than other mitigation methods.

Implementation Method 1

A capacitor couples the plating stub to a ground layer

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8830690B2Minimizing plating stub reflections in a chip package using capacitance
Publication Date: 2014.09.09 LENOVO INT LTD
  • US8830690B2 patent drawing
  • US8830690B2 patent drawing
  • US8830690B2 patent drawing

AI summary

Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.