Platinum Interlayer Semiconductor Via Hole Stability
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Solution Overview
Problem
The connection between the surface side electrode and the back electrode in semiconductor devices can become unstable due to deformation during mounting, leading to unreliable contact and operational instability.
Innovation Solution
A semiconductor device design featuring a via hole connection using a platinum metal layer that is chemically stable to etching gases, forming a reaction layer with the semiconductor layer, and an interlayer that ensures a stable electrical connection, preventing void formation and deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a metal layer (AuGeNiAu alloy) is used as the surface side electrode, then the electrode can be simultaneously formed with the ohmic electrode, but the electrode deforms with heat during mounting, causing unstable contact
Solution Approach 1:
The patent changes the material parameter of the surface side electrode from a multi-layer AuGeNiAu alloy to a single-layer platinum (Pt) film. This material substitution fundamentally alters the thermal and chemical properties, making the electrode resistant to deformation during heat-based mounting processes while maintaining ease of formation through standard sputtering techniques.
Solution Approach 2:
The patent creates a composite structure where the platinum surface side electrode forms a platinum silicide reaction layer with the semiconductor substrate. This composite material system combines the high heat resistance and chemical stability of platinum with the electrical properties needed for electrode function, preventing deformation while ensuring stable contact.
2Manufacturing precision
If RIE etching with chlorine-containing gas is used to form via holes, then selective etching is achieved, but the metal layer reacts with the etching gas, forming voids and causing deformation
Solution Approach 1:
The patent converts the potential harmful reaction between metal and chlorine etching gas into a beneficial outcome by selecting platinum, which is chemically inert to chlorine. This eliminates void formation and deformation caused by gas-metal reactions, while the platinum's catalytic properties actually enhance the etching process uniformity.
Solution Approach 2:
The platinum metal layer creates a chemically inert environment during the RIE etching process. Since platinum does not react with chlorine-containing etching gases, it protects the underlying semiconductor structure from unwanted reactions and prevents void formation, allowing the etching to proceed cleanly and uniformly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable and reliable electrical connection between the surface side electrode and the back electrode, enhancing the semiconductor device's operational stability and reliability by using a platinum metal layer that does not react with etching gases, thus preventing void formation and deformation.
Implementation Method 1
an alloy reaction layer formed below the metal layer as a result of an alloy reaction between the semiconductor substrate and the metal layer
Implementation Method 2
A hole of the via hole is formed by etching the semiconductor layer selectively using an RIE (Reactive Ion Etching) method, for example. Etching gas contains chlorine, for example.
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3C
AI summary
A semiconductor device concerning the embodiment includes a semiconductor layer (20) which has a first surface and a second surface which is opposite to the first surface, an interlayer (40) which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer (30) which covers an inside of a hole (17) which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.