PLB Bridge Command Translation for FPGA Data Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of Field Programmable Gate Arrays (FPGAs) is limited by the disparity between the operating parameters of embedded processors and the FPGA fabric, leading to bottlenecks in operations such as memory access, and the integration of ASIC cores reduces flexibility and yield compared to standalone ASICs.
Innovation Solution
Incorporating a slave processor local bus bridge with a crossbar switch and dynamic bus sizing to translate burst commands between different bus widths, allowing access to buffer space and optimizing data transfer through the FPGA fabric without significant loss of design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If embedded processors are designed apart from PLDs and coupled directly to FPGA fabric, then processor operating frequency and performance parameters are improved, but disparity between processor operating parameters and FPGA fabric parameters causes performance bottlenecks
Solution Approach 1:
The patent introduces a bridge circuit as an intermediary component between the embedded processor and FPGA fabric. This bridge translates commands between the processor's native bus protocol and the FPGA fabric's bus protocol, enabling efficient communication despite parameter disparities. The bridge acts as a mediator that resolves the incompatibility between the high-speed processor interface and the FPGA fabric interface, eliminating the performance bottleneck while preserving the processor's high operating frequency.
2Productivity
If ASIC cores are integrated into FPGAs to enhance performance, then data throughput is improved, but design flexibility and manufacturing yield are reduced
Solution Approach 1:
The patent implements dynamic bus sizing capability that allows the bus width to be programmably adjusted between 32-bit and 128-bit modes. This dynamic adaptability enables the system to optimize data throughput by selecting appropriate bus widths based on specific application requirements, while maintaining design flexibility through programmable configuration rather than fixed hardwired connections. The dynamic nature of the bus interface resolves the contradiction between high throughput and flexibility.
3Device complexity
If fixed bus width interfaces are used between processor and FPGA fabric, then interface complexity is reduced, but data transfer efficiency is limited
Solution Approach 1:
The patent creates a universal bus interface that can operate with multiple bus widths (32-bit, 64-bit, 128-bit) and support different command types (burst commands, non-burst commands) through a single unified architecture. The bridge circuit is designed to handle various data transfer scenarios using the same interface structure, eliminating the need for multiple specialized interfaces. This multi-functionality improves data transfer efficiency across different scenarios while keeping the interface design manageable through standardized protocols.
4Productivity
If burst commands are translated to match FPGA fabric buffer requirements, then data transfer optimization is improved, but additional processing latency is introduced
Solution Approach 1:
The patent implements a command buffer that pre-loads and queues burst commands before they need to be executed. By preparing commands in advance and organizing them in the buffer according to FPGA fabric buffer requirements, the system minimizes real-time translation latency during actual data transfer operations. The preliminary organization of commands allows for more efficient execution while reducing the perceived latency, as the translation work is performed in advance rather than in real-time during critical data transfer windows.
Data Source
AI summary
Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.