PLC Program Analysis Using SMT Counterexamples for Debugging
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Solution Overview
Problem
Current methods for debugging Programmable Logic Controller (PLC) programs, such as simulation and model-checking, are not exhaustive, time-consuming, and require significant human intervention, making it difficult to guarantee that all execution configurations are tested and errors are fully understood.
Innovation Solution
A method that translates a PLC program into a logical framework, determines properties, uses automated solvers to verify satisfiability, and translates counter-examples into error configurations, allowing for automated and exhaustive debugging by simulating error scenarios and providing detailed information on error causes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation method is used for debugging PLC programs, then debugging can be performed before production implementation, but the method is not exhaustive and time-consuming
Solution Approach 1:
The patent replaces manual simulation-based debugging with an automated model-checking system that uses formal verification algorithms to exhaustively analyze all possible execution paths of the PLC program, eliminating the need for time-consuming manual test case execution while ensuring complete debugging coverage
Solution Approach 2:
The patent performs debugging analysis before production implementation by translating the PLC program into a formal model and using model-checking to verify correctness in advance, identifying all potential bugs including those in untested execution paths before the program is deployed to actual hardware
2Loss of time
If model-checking method is used to save time and resources, then execution time is reduced, but testing efficiency is limited by CPU time and still not exhaustive
Solution Approach 1:
The patent segments the PLC program into a formal mathematical model that can be systematically analyzed by the model-checker, breaking down the complex program into states and transitions that can be exhaustively verified within computational limits, thereby achieving both time efficiency and completeness
Solution Approach 2:
The patent changes the parameter of analysis from executing actual program code to verifying formal logical properties of the program model, allowing exhaustive analysis of all possible executions without being constrained by CPU time required for actual program execution
3Ease of operation
If manual test development and execution is performed, then some configurations can be manually defined, but output values must be analyzed by programmers and it is hard to understand the fundamental reason of the error
Solution Approach 1:
The patent provides automated feedback that includes not only the detection of errors but also the generation of counter-examples showing specific input configurations that lead to errors, and explains the fundamental reasons by tracing which program statements cause the property violations, eliminating the need for programmer analysis
Data Source
AI summary
It is disclosed a PLC Program analysis method where a program (PROG) is translated (TRANS) into a model (MOD) in a logical framework, from which properties (Prop) are determined. Said properties coupled with user specifications (IntProp) are verified by an automated solver (SMT). If contraposition of a property (Prop) is satisfiable, counter-examples (PROOF NOK) representative of model inputs and internal memory values is provided. Counter-examples (PROOF NOK) are translated into error initial configurations (IniConf) of said model. Execution of the model is simulated (EXE) with said model error initial configurations (IniConf), and error intermediary configurations (AST-IntConf) of said model simulation are recorded up to said property violation. Error initial and intermediary configurations (Lad-IniConf, Lad-IntConf) of said original program (PROG) are derived from error initial configurations (IniConf) of said model and error intermediary configurations (AST-IntConf) of said model simulation and displayed. An apparatus for executing said method is provided.