Multi-CPU PLC Backplane Access via Time Slot Allocation
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Solution Overview
Problem
Existing PLC systems face challenges in achieving real-time access to slave modules due to signal conflicts and inefficiencies in token-based control methods, which hinder performance in real-time control scenarios.
Innovation Solution
A PLC system with multiple CPU modules that allocate time slots for access to a backplane, where each CPU module detects clock signals to avoid collisions and synchronizes time counts to reduce standby times, allowing for efficient and synchronized access to slave modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a token-based control method is used for backplane access in a multi-master PLC system, then control rights are allocated according to predetermined rules, but real-time control performance deteriorates due to token exchange time and processing delays
Solution Approach 1:
The patent segments the continuous backplane access time into discrete time slots, with each CPU module allocated specific time slots for access. This eliminates the need for token exchange between masters, as each master knows its predetermined access windows. The segmentation of time resources directly resolves the contradiction by removing token processing delays while maintaining reliable control right allocation through the structured time slot assignment.
2Loss of time
If time slots are allocated for backplane access to reduce token exchange time, then real-time control performance improves, but signal collisions may occur due to clock errors in multi-master systems
Solution Approach 1:
The patent introduces a slave module as an intermediary that generates clock signals during its active time slot. When a master CPU module detects this clock signal from the slave, it recognizes that the slave is currently accessing the backplane and refrains from accessing simultaneously. This intermediary clock signal mechanism prevents collisions caused by clock errors, as the slave's active state serves as a reliable indicator that overrides potential timing drift issues among multiple masters.
3Productivity
If multiple CPU modules access the backplane simultaneously, then processing speed increases, but signal conflicts are generated that disable normal access
Solution Approach 1:
The patent implements periodic action by allocating specific time slots to each CPU module for backplane access. Instead of allowing simultaneous random access that causes conflicts, each master CPU module accesses the backplane periodically during its assigned time slots. This structured periodic access pattern enables multiple CPUs to share the backplane efficiently without signal conflicts, maintaining both high productivity through parallel processing opportunities and reliable conflict-free operation.
Data Source
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AI summary
Disclosed is a PLC system having a plurality of CPU modules and a control method thereof, wherein the method includes ascertaining a clock signal when a count is a count corresponding to a time slot allocated by a master CPU module, generating a clock signal by accessing to a backplane, and ending generation of clock signal at a time when the access to the backplane ends.