PLC Reception via Chirp Phase Detection on Multi-Core Processors
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Solution Overview
Problem
Existing power line communication (PLC) systems in tractor-trailers rely on hardware circuits for decoding and encoding, which are costly and dependent on specific hardware components, limiting flexibility and increasing costs.
Innovation Solution
Implementing software algorithms in multiple co-processors to decode and encode PLC signals, utilizing a general timer module to perform real-time decoding without additional hardware, by comparing successive chirp waveforms to determine phase changes and reconstruct digital bit streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware circuits are used for decoding and encoding PLC signals, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces hardware circuit implementations with software algorithms executed on general-purpose processors. Specifically, the PLC signal decoding function is implemented as software that processes digitized waveform samples, comparing successive chirp waveforms to detect phase changes and reconstruct digital bit streams. This substitution eliminates complex hardware circuits while maintaining decoding functionality and reliability.
2Productivity
If hardware circuits are used for PLC communication, then processing speed is improved, but cost and device complexity increase
Solution Approach 1:
The patent implements PLC signal processing as software running on general-purpose processors with co-processors for parallel computation. The software efficiently processes digitized waveform samples by comparing successive chirps to detect phase changes, achieving real-time processing speeds without requiring specialized hardware circuits. This approach reduces device complexity while maintaining processing capability.
Solution Approach 2:
The patent divides the signal processing task into multiple segments handled by different co-processors. One co-processor creates the digital waveform from analog PLC messages, another predicts phase changes by comparing chirps, and a third reconstructs the digital bit stream. This segmentation enables parallel processing that maintains speed while using software rather than complex hardware.
3Measurement precision
If specialized hardware components are used, then measurement precision is improved, but adaptability and ease of manufacture worsen
Solution Approach 1:
The patent implements PLC communication functionality as software that can run on general-purpose processors, making the system adaptable to different hardware platforms and configurations. The software algorithm for detecting phase changes by comparing successive chirp waveforms can be deployed on various processor types without requiring specialized hardware components, thereby improving adaptability while maintaining measurement precision through software-based waveform analysis.
Solution Approach 2:
The patent uses software to dynamically adjust processing parameters such as sampling rates, threshold values for phase change detection, and waveform comparison algorithms. This flexibility allows the system to adapt to different PLC signal characteristics and communication conditions without requiring physical hardware changes, thereby improving both adaptability and ease of manufacture.
Data Source
AI summary
A system and method for power line communication (PLC) reception are provided. In one embodiment, a tractor controller is provided comprising a main processor, a first co-processor, a second co-processor, and third co-processor. The first co-processor is configured to create a digital waveform from an analog power line communication (PLC) message received from a trailer via a power line. The second co-processor is configured to: for each of a plurality of chirps in the digital waveform, compare a given chirp with a previous chirp to predict whether a phase change occurred; and create a digital bit stream representing the PLC message from the predictions. The third co-processor is configured to process the digital bit stream and send the digital bit stream to the main processor. Other embodiments are provided.