PLC Command Compilation Scheme Optimization
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Solution Overview
Problem
Existing Programmable Logic Controllers (PLCs) lack flexibility in processing rate and program size, requiring system upgrades or new versions when performance is inadequate, as they only support fixed processing rates and program sizes, limiting adaptability to varying system characteristics.
Innovation Solution
A method for dynamically optimizing PLC command compilation by allowing users to choose between processing rate and size options, using direct or indirect compile schemes based on a command map table, to generate optimized object codes for improved performance and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed processing rate and fixed program size are supported in PLC, then system simplicity is maintained, but flexibility and adaptability to varying system characteristics are lost
Solution Approach 1:
The patent implements dynamic compile processing schemes that can switch between different compilation modes (rate-optimized and size-optimized) based on user selection. The system dynamically adjusts compilation parameters and processing methods rather than being fixed, allowing the PLC to adapt to different performance requirements without hardware changes.
Solution Approach 2:
The patent changes compilation parameters such as optimization level, code generation mode, and resource allocation based on the selected scheme. By modifying these parameters during the compilation process, the system can optimize for either processing rate or program size depending on user needs, thereby achieving flexibility without increasing device complexity.
2Productivity
If direct compile processing scheme is used for simple commands, then processing rate is improved, but program size may increase
Solution Approach 1:
The patent applies different compilation strategies to different parts of the program based on command complexity. Simple commands use direct compile processing for optimized execution speed, while complex commands use indirect processing. This localized approach ensures that processing rate is improved where needed without unnecessarily increasing program size across the entire system.
Solution Approach 2:
The patent applies direct compilation selectively to only those commands that benefit from it (simple, frequently executed commands), rather than applying it universally. This partial action approach optimizes processing rate for critical paths while avoiding the program size overhead of direct compilation for all commands.
3Quantity of substance
If indirect compile processing scheme with command map table is used, then program size is reduced through function copying, but processing rate may decrease due to additional lookup steps
Solution Approach 1:
The patent segments the compilation process into distinct phases: command identification, map table lookup, function copying, and execution. By separating these steps, the system can optimize for program size through selective function copying while minimizing the impact on processing rate through efficient segmentation of critical and non-critical operations.
4Productivity
If PLC is replaced with upper version or system is changed to achieve higher processing rate or larger program size, then performance requirements are met, but system complexity and cost increase
Solution Approach 1:
The patent makes a single PLC system universal by implementing multiple compile processing schemes within the same device. The system can function in different modes (rate-optimized or size-optimized) based on user selection, eliminating the need for multiple PLC versions or system replacements to meet different performance requirements.
Data Source
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AI summary
The present disclosure provides a method of compiling a PLC (Programmable Logic Controller) command, the method including: determining one compile processing scheme chosen from a plurality of compile processing schemes for a command contained in a program to be executed in a PLC; and executing a command compile optimized for a rate or a size based on the chosen compile processing scheme.