PLC High-Speed Counter Buffering to Cut Interrupt Branching
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Solution Overview
Problem
Conventional PLC high speed counters experience performance degradation and increased interrupt processing time due to excessive resource occupation and complex branching processes when handling high-speed pulse trains, leading to potential missed counts and software capacity issues.
Innovation Solution
The PLC high speed counter employs an operating method that calculates and stores current values in a buffer, determining the counter mode only upon request from an external device, using a linear count manner and an equation to convert values for the ring counter mode, thereby reducing unnecessary branching and interrupt processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLC high speed counter determines the counter mode (linear or ring) in the interrupt routine every time a pulse train is input, then the counter can accurately handle both modes, but the interrupt processing time increases and performance degrades
Solution Approach 1:
The counter mode is determined in advance during system initialization or configuration, not during each interrupt occurrence. The mode determination result is stored and reused for subsequent counting operations, eliminating the need to re-determine the mode on every pulse input.
Solution Approach 2:
The mode determination logic is extracted from the time-critical interrupt routine and placed in the non-time-critical main program or configuration routine. This separates the mode determination function from the pulse counting function, allowing the interrupt handler to focus solely on accurate and fast counting.
2Adaptability or versatility
If the PLC high speed counter implements complex branching processes to handle different counter modes, then it can support multiple operating modes, but the software capacity increases and processing speed decreases
Solution Approach 1:
The counter uses a unified counting mechanism that dynamically adapts to different modes through configuration parameters rather than through complex branching logic. The same core counting code handles both linear and ring modes by referencing mode-specific parameters stored in memory.
Solution Approach 2:
A single counting routine is designed to handle both linear and ring counter modes universally. The routine uses configuration parameters and memory-stored mode information to determine the appropriate counting behavior, eliminating the need for separate handling code for each mode.
3Measurement precision
If the PLC high speed counter performs frequent interrupt processing for high-speed pulse trains, then it can accurately count high-speed pulses, but the microprocessor resources are excessively occupied
Solution Approach 1:
The counting function is segmented into hardware-level interrupt handling for pulse detection and software-level processing for value retrieval. The interrupt handler performs only the essential pulse detection and counter update, while the main program handles mode determination and current value calculation, reducing interrupt frequency and duration.
Solution Approach 2:
The high-speed counter hardware automatically performs pulse detection and counting without requiring frequent microprocessor intervention. The counter operates autonomously during pulse input, and the microprocessor is only engaged when the current value is requested, allowing the system to serve itself during critical counting operations.
Data Source
AI summary
Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value.