PLC CPU Parallel I/O via Segmented Memory Banks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The architecture of a Programmable Logic Controller (PLC) using a general-purpose microprocessor differs significantly from that of a general-purpose computer, making parallel input/output operations through the PLC system bus and field network inefficient.
Innovation Solution
A CPU unit for the PLC is configured with a microprocessor, memory, and dual communication circuits for the PLC system bus and field network, enabling parallel execution of input/output processes using a system program that manages data transfer and control program execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a general-purpose microprocessor is used in the PLC CPU unit, then the architecture becomes closer to general-purpose computers (reducing development burden and cost), but the ability to efficiently perform parallel input/output operations through the PLC system bus and field network deteriorates
Solution Approach 1:
The patent divides the data memory into multiple independent banks (first data memory bank and second data memory bank) that can be accessed simultaneously by different communication circuits. This segmentation allows the PLC system bus controller and field network controller to operate in parallel without interfering with each other, thus maintaining high productivity while using a general-purpose microprocessor architecture.
Solution Approach 2:
The patent introduces an arbiter as an intermediary component that manages access to the data memory banks. The arbiter coordinates between the PLC system bus controller and field network controller, enabling efficient parallel access to different memory banks. This mediator ensures that the general-purpose microprocessor can handle multiple communication protocols and architectures simultaneously without performance degradation.
2Adaptability or versatility
If identical data memory is accessed through an arbiter for multiple purposes (I/O bus transfer, network transfer, control program execution), then memory sharing is achieved, but the architecture diverges significantly from general-purpose computer design
Solution Approach 1:
The data memory is segmented into multiple independent banks, each accessible by different controllers. This segmentation allows simultaneous access without requiring a complex arbiter-mediated shared memory system, thereby reducing architectural complexity while maintaining versatility. The first data memory bank serves the PLC system bus, while the second data memory bank serves the field network, enabling independent parallel operations.
Data Source
AI summary
A microprocessor controls at least one of a first communication circuit and a second communication circuit such that a first input/output process and a second input/output process are executed in parallel. The first input/output process includes a process outputting output data from a first transfer buffer, through the first communication circuit, to a first instrument in a PLC system bus, and a process inputting input data from the first instrument, through the first communication circuit, to the first transfer buffer. The second input/output process includes a process outputting output data from a second transfer buffer, through the second communication circuit, to a second instrument in a field network, and a process inputting input data from the second instrument, through the second communication circuit, to the second transfer buffer.