PLC I/O Logging for Synchronized Analog and Count Capture
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Solution Overview
Problem
The programmable logic controller (PLC) described in Patent Literature 1 has a processing speed constraint due to the CPU's reading time, which results in longer processing times and reduced tact time in production devices, as the synchronizing control signal period must be longer than the CPU's reading time for both count and analog signal values, and lacks multiple storage areas, requiring data to be read from a single storage area before it is overwritten.
Innovation Solution
An input/output control unit with a storage, input/output controller, and logger blocks that store information in preset storage areas in synchronization with a trigger signal, allowing simultaneous storage of digital and count information, reducing the need for CPU reading and enabling shorter trigger signal periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU unit reads count values and analog signal values in every period of the synchronizing control signal, then the processing is synchronized, but the period of the synchronizing control signal must be longer than the CPU reading time, which increases processing time and reduces productivity
Solution Approach 1:
The patent divides the storage function into multiple storage areas within the input/output controller, allowing different data types (count values, analog signal values) to be stored in separate areas. This enables parallel access and eliminates the need for sequential reading by the CPU, thus reducing the synchronizing control signal period while maintaining synchronization accuracy.
Solution Approach 2:
The patent introduces an intermediary storage structure (multiple storage areas in the input/output controller) between the sensors/encoders and the CPU. This intermediary allows data to be prepared and organized before CPU access, reducing the CPU's reading time and enabling shorter synchronizing control signal periods without sacrificing data integrity.
2Device complexity
If a single storage area is used in the internal memory, then the structure is simple, but data must be read before being overwritten, which increases processing time
Solution Approach 1:
The patent segments the single storage area into multiple storage areas within the input/output controller's memory. This allows simultaneous reading and writing operations in different areas, eliminating the time loss associated with sequential read-before-write operations while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent implements preliminary action by pre-organizing data in multiple storage areas before CPU access is needed. Data are prepared in advance in separate storage areas, so when the CPU needs to read, the data are already available without requiring a read-before-write sequence, thus reducing processing time.
Data Source
AI summary
An input/output control unit (120) includes a storage, an input/output controller (126), an analog signal input interface (129), and a pulse signal input interface (127A). The input/output controller (126) includes a pulse signal input block (1411) to generate a trigger signal, an A/D conversion block (1431) to generate wafer thickness information by analog-to-digital conversion of an analog signal, a logger block (1501) to, in synchronization with the trigger signal, store the wafer thickness information a preset table A in the storage, a counter block (1461) to continuously generate, from the digital signal, count value information indicating a count value and output the generated information, and a logger block (1502) to, in synchronization with the trigger information, store the count value information, in association with the wafer thickness information, in a table TB in the storage (124).