PLC Simulator Memory Access Coordination via Execution Status Flags

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Solution Overview

Problem

Memory access contention between a Programmable Logic Controller (PLC) and external devices in PLC simulation systems can lead to unintended operations, reducing the reliability of the simulation system.

Innovation Solution

A PLC simulation system with a socket interface for communication between the PLC simulator and external simulator, using notification commands and detection units to manage program execution status, such as updating counters or flags, to prevent simultaneous access to the PLC memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the PLC and external devices communicate with each other by accessing the memory content, then the functionality and versatility of the PLC simulation system is improved, but access contention occurs between the PLC and external device, causing unintended operations and reducing reliability

Engineering Contradiction:
Improvecommunication functionalityVSAvoidaccess reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

A flag memory area is introduced as an intermediary between the PLC and external devices. The PLC sets a flag when memory access is in progress, and external devices check this flag before accessing memory. This intermediary mechanism coordinates access without requiring complex locking protocols, maintaining both communication functionality and access reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system uses a flag-based feedback mechanism where the PLC provides real-time status information about memory access state to external devices. External devices continuously monitor the flag and adjust their access behavior accordingly, creating a feedback loop that prevents access contention while maintaining system versatility.

Inventive Principle:
Principle #23Feedback

2Productivity

If the PLC simulator and external simulator operate independently with parallel execution, then the productivity and efficiency of the simulation system is improved, but simultaneous access to PLC memory may occur, causing unintended operations

Engineering Contradiction:
Improvesimulation efficiencyVSAvoidmemory access safety
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The PLC simulator performs preliminary action by setting the flag memory area to indicate memory access state before actual memory operations occur. This preliminary signaling allows the external simulator to plan and timing its access requests accordingly, maintaining parallel execution efficiency while preventing simultaneous access conflicts.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The external simulator periodically checks the flag memory area status before attempting memory access operations. This periodic monitoring approach allows both simulators to operate in parallel while ensuring that memory access safety is maintained through rhythmic status verification and coordinated access timing.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP2816427B1PLC simulation system, PLC simulator, recording medium, and simulation method
Publication Date: 2021.07.28 OMRON CORP
  • EP2816427B1 patent drawingFigure 1
  • EP2816427B1 patent drawingFigure 2~3
  • EP2816427B1 patent drawingFigure 4~5

AI summary

In a PLC simulation system (10), at least one of a PLC simulator (2) and an external simulator (4) executes processing while checking the status of program execution in the other. For example, the PLC simulator (2) provides a socket interface, and operates upon receiving various commands from the external simulator (4). The external simulator (4) checks, using a command, whether processing for a program is being executed or the execution is finished in the PLC simulator (2). The external simulator (4) checks the status of operation of the program in the PLC simulator (2), and executes processing accompanying writing to a PLC memory (205b) or the like, in a case where contention of access to the PLC memory (205b) does not occur.