PLC Shared Memory Segmentation for Data Consistency
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Solution Overview
Problem
In programmable logic controllers (PLCs) for factory automation, the inconsistency in data transfer between the CPU and network unit due to differing cycle times leads to data loss, as the network unit is forced to wait for the CPU to complete read operations, causing overwritten data in the receive buffer, which cannot be written to the shared memory, resulting in missing data for the CPU.
Innovation Solution
A PLC configuration with a shared memory divided into two areas: one for data consistency and another for real-timeliness, where the CPU transfers data from these areas at different intervals, ensuring that data for which consistency is crucial is handled under exclusive control, and data for real-timeliness is transferred at a separate period, reducing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the network unit waits for the CPU to complete read operations before writing data to shared memory, then data consistency is improved, but data loss increases due to overwritten receive buffer data
Solution Approach 1:
The patent divides the shared memory into two distinct areas: a first data area for data requiring consistency (accessed under exclusive control) and a second data area for data requiring real-timeliness (accessed without exclusive control). This segmentation allows the system to handle different data types with different access patterns, preventing data loss in the receive buffer while maintaining consistency where needed.
Solution Approach 2:
Different quality attributes are applied to different parts of the shared memory. The first data area prioritizes data consistency with exclusive access control, while the second data area prioritizes real-timeliness with concurrent access allowed. This local differentiation resolves the contradiction by allowing the network unit to write to the second area without waiting for CPU read operations.
2Productivity
If the CPU reads data from shared memory during network unit write operations, then productivity is improved, but data consistency deteriorates
Solution Approach 1:
The shared memory is segmented into a first data area where exclusive control maintains consistency during CPU reads, and a second data area where concurrent access improves productivity. This segmentation allows simultaneous operations in different areas, resolving the contradiction between productivity and consistency.
Solution Approach 2:
The patent introduces a flag mechanism as an intermediary to coordinate access to the first data area. The flag indicates whether the CPU is in a read operation, allowing the network unit to determine when it can safely write without compromising consistency, while still enabling efficient data transfer.
3Reliability
If the network unit uses exclusive control with flags to prevent concurrent access, then data consistency is improved, but device complexity increases
Solution Approach 1:
The patent segments the shared memory access control mechanism: the first data area uses flag-based exclusive control for consistency-critical data, while the second data area allows concurrent access without flags. This segmentation reduces overall complexity by applying exclusive control only where necessary.
Solution Approach 2:
Different control qualities are applied locally: exclusive control with flags is applied only to the first data area where consistency is critical, while the second data area uses simpler concurrent access. This local differentiation reduces device complexity while maintaining consistency where needed.
4Ease of operation
If the CPU transfers data at a single fixed interval, then ease of operation is improved, but data loss increases for real-time data
Solution Approach 1:
The patent segments the data transfer operation into two separate transfer processes: one for the first data area and another for the second data area. Each process can operate at different intervals appropriate to the data type, reducing data loss for real-time data while maintaining simplicity through separate, dedicated transfer routines.
Solution Approach 2:
The patent introduces dynamic transfer intervals for different data areas. The CPU can transfer data from the first data area at one interval and from the second data area at another interval, allowing flexible adaptation to different data requirements while maintaining operational simplicity through structured transfer processes.
Data Source
AI summary
A received-data writer of a network unit records first data in a first data area when a flag is set indicating that a write is allowed, and records second data in a second data area. The first data are data for which data consistency is to be guaranteed among received data that is received from the first slave station and a second slave station, and the second data are data for which real-timeliness is to be guaranteed among the received data. A first transferrer of a CPU transfers the first data recorded in the first data area to a first storage at an interval of a first transfer period when the flag is set indicating that a read is allowed. A second transferrer of the CPU transfers the second data recorded in the second data area to a second storage at an interval of a second transfer period.