Priority-Based Program Sequencing for PLC Task Preemption

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Solution Overview

Problem

In programmable logic controllers, high-priority events or program parts are often delayed due to long-running low-priority processes occupying available arithmetic logic units, leading to inefficient resource utilization and potential blocking of higher priority tasks.

Innovation Solution

A method and apparatus that allow for priority-based control of program part execution, enabling higher priority program parts to interrupt and take over arithmetic logic units from lower priority ones, with the operating control managing these interruptions and ensuring seamless continuation of interrupted tasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If low-priority processes occupy arithmetic logic units for long durations, then resource utilization by lower priority tasks is improved, but high-priority task execution is delayed

Engineering Contradiction:
Improveresource utilizationVSAvoidhigh-priority task delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic priority-based preemption where the scheduling behavior of arithmetic logic units changes based on the priority of incoming events. When a high-priority event arrives, the system dynamically switches from cooperative multitasking to preemptive scheduling, allowing the high-priority task to immediately occupy the arithmetic logic unit regardless of ongoing low-priority operations. This dynamic adjustment resolves the contradiction by making resource allocation flexible rather than static.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The operating control acts as an intermediary between events and arithmetic logic units, managing the allocation and preemption of computational resources. It monitors the priority levels of pending events and intervenes to reassign arithmetic logic units from low-priority to high-priority tasks when needed. This intermediary mechanism enables the system to balance resource utilization with timely high-priority task execution.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If multiple arithmetic logic units operate in parallel independently, then processing speed is improved, but resource coordination and communication overhead increase

Engineering Contradiction:
Improveprocessing speedVSAvoidresource coordination
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The operating control serves multiple functions simultaneously: it acts as an event manager, a scheduler, a preemption controller, and a coordination hub for multiple arithmetic logic units. This multi-functional design allows the system to maintain parallel processing speed while consolidating coordination responsibilities in a single controlling entity, thereby managing complexity efficiently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements feedback mechanisms where the operating control continuously monitors the state of arithmetic logic units and the queue of pending events. Based on this feedback, it dynamically adjusts the allocation of computational resources, ensuring that parallel operations are coordinated efficiently and that high-priority tasks receive timely access to required arithmetic logic units.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20230409001A1Method and device for controlling the sequence of program parts, programming method, programming device
Publication Date: 2023.12.21 SCHNEIDER ELECTRIC IND SAS
  • US20230409001A1 patent drawing
  • US20230409001A1 patent drawing
  • US20230409001A1 patent drawing

AI summary

A method of controlling the sequence of program parts has the following steps: initiated by the occurrence of a first event (E1), executing a first program part (P1) on a first arithmetic logic unit (RW1), wherein the first event (E1) and/or the first program part (P1) is/are assigned a first priority (Py1), and initiated by the occurrence of a second event (E2), interrupting the execution of the first program part (P1) and then executing a second program part (P2) on the first arithmetic logic unit (RW1), wherein the second event (E2) and/or the second program part (P2) is/are assigned a second priority (Py2) that is higher than the first priority (Py1), wherein the first and/or the second program part (P1, P2) is/are a function block in the sense of IEC 61499 or a part thereof or a data transmission initiated thereby.