PLC Program Verification Using Timing Charts and Counterexamples

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Solution Overview

Problem

Debugging Programmable Logic Controllers (PLCs) is challenging due to the inefficiency of existing verification methods for timing chart specifications, which are not exhaustive and costly, especially in industrial settings where bugs can cause significant human and material damages.

Innovation Solution

A computer-implemented method that translates PLC programs into models, integrates temporal functional specifications, computes abstract semantics, performs predicate transformation, and deduces properties to verify compliance with timing charts, providing an exhaustive guarantee and counter-examples to detect and correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If testing is used to verify PLC programs, then implementation complexity is reduced, but verification exhaustiveness deteriorates and debugging time increases

Engineering Contradiction:

Improveverification method complexityVSAvoidverification exhaustiveness

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent replaces the mechanical execution-based testing approach with a formal deductive verification system using mathematical logic and automated theorem proving. This substitution transforms the verification process from empirical testing to rigorous logical deduction, achieving exhaustiveness without proportionally increasing implementation complexity through specialized software tools.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary formal specification layer (timing charts with temporal logic) between the PLC program and verification process. This intermediary enables automated deductive verification by providing precise mathematical descriptions of expected behavior, bridging the gap between program code and verification goals while maintaining exhaustiveness.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If model-checking is used to verify timing charts, then verification exhaustiveness improves, but CPU time consumption increases

Engineering Contradiction:

Improveverification exhaustivenessVSAvoidCPU time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by computing abstract semantics and generating verification conditions before actual verification. This preprocessing step transforms the verification problem into a form suitable for efficient automated solving, reducing the computational burden during the actual verification phase while maintaining exhaustiveness.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the verification process into distinct phases: translating PLC program to automaton, computing abstract semantics, generating verification conditions, and solving. This segmentation allows each phase to be optimized independently, reducing overall CPU time consumption while maintaining verification exhaustiveness through systematic decomposition of the complex verification task.

Inventive Principle:

Principle #1Segmentation

3Reliability

If deductive verification is used to check PLC programs, then verification exhaustiveness is guaranteed, but implementation complexity increases

Engineering Contradiction:

Improveverification exhaustivenessVSAvoidverification system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by automating the entire deductive verification process through specialized software that automatically translates PLC programs, computes abstract semantics, generates verification conditions, and performs logical deduction. This automation eliminates the need for manual formal verification efforts, making the complex deductive verification process accessible without requiring expert intervention.

Inventive Principle:

Principle #25Self-service

4Difficulty of detecting and measuring

If extensive testing is performed to detect bugs, then bug detection capability improves, but debugging time and cost increase

Engineering Contradiction:

Improvebug detection capabilityVSAvoiddebugging time

Core Design Contradiction:

Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The patent replaces extensive manual testing and debugging with automated deductive verification that mathematically proves correctness. This substitution detects verification failures through logical contradiction rather than empirical testing, dramatically reducing debugging time while maintaining or improving bug detection capability through exhaustive logical analysis.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP4047482A1Improved checking of correctness of a PLC program

Publication Date: 2022.08.24 MITSUBISHI ELECTRIC R&D CENTRE EUROPE BV

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AI summary

The present invention is related to a method for checking correctness of a PLC program described by functional specifications typically presented as a timing chart. The method comprises: - S1: translating the PLC program into a model, - S2: translating the timing chart and integrating said timing chart into the model, - S3: computing abstract semantics, to infer information eventually missing in the timing chart, - S4: predicating transformation, and deducing properties to be verified, from the model and from predefined PLC formalized instructions, in order to satisfy timing chart verification, - S5: solving and checking whether said properties are always verified, or providing counter-examples, - S6: translating said counter-examples into PLC model errors events initial configurations, - S7: simulating execution, - S8: assembling states and events executions variables values, and - S9: translating back to PLC program.