PLCP Header Encoding for Early Cyclic Prefix Mode Decoding

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Solution Overview

Problem

Block-based communication systems, such as OFDM, face inefficiencies in bandwidth utilization and increased latency due to the fixed guard interval duration, which is derived based on worst-case channel conditions, leading to reduced throughput.

Innovation Solution

A new PLCP header format is encoded with block-coded cyclic prefix mode bits, allowing early decoding of CP mode information, enabling the receiver to process payload symbols before complete header decoding, by using a systematic Reed-Salomon encoder and block code to split and map the header into multiple symbols, including CP mode bits in the first symbol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the guard interval time duration is increased to handle worst-case channel conditions, then the system robustness is improved, but the bandwidth efficiency is reduced

Engineering Contradiction:
Improvesystem robustnessVSAvoidbandwidth efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic adaptation of the guard interval time duration based on actual channel conditions. The system transitions from a static guard interval (based on worst-case conditions) to a dynamic guard interval that adjusts according to measured channel characteristics, thereby improving bandwidth efficiency while maintaining system robustness when needed.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the PLCP header is decoded completely before processing payload symbols, then the decoding accuracy is improved, but the processing latency is increased

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the PLCP header decoding process into two independent parts: CP mode decoding and full header decoding. The CP mode bits are extracted and decoded separately from the main header, allowing the receiver to determine the guard interval duration and begin processing payload symbols before completing the full header decoding. This segmentation maintains decoding accuracy while significantly reducing processing latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary decoding of the CP mode bits from the PLCP header before completing the full header decoding process. By extracting and decoding the CP mode information in advance, the receiver can determine the guard interval duration and start processing payload symbols earlier, thereby reducing overall processing latency without compromising the accuracy of the complete header decoding.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the fixed guard interval duration is used for all channel conditions, then the implementation complexity is reduced, but the throughput is decreased

Engineering Contradiction:
Improveimplementation complexityVSAvoidsystem throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces dynamic guard interval adaptation while maintaining relatively simple implementation. The system uses channel quality measurements to select from a set of predefined guard interval durations, avoiding complex real-time optimization while still achieving significant throughput improvements compared to fixed guard interval approaches.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP2409441B1Techniques for encoding PLCP headers
Publication Date: 2015.07.29 KONINKLIJKE PHILIPS NV
  • EP2409441B1 patent drawingFigure 1~2
  • EP2409441B1 patent drawingFigure 3
  • EP2409441B1 patent drawingFigure 4

AI summary

A method (400) and apparatus for encoding a block-based communication system header. A physical (PHY) layer header and a medium access control (MAC) header of the block-based communication system header are encoded to generate parity bits, wherein the PHY layer header includes at least cyclic prefix (CP) mode bits (S410). Parity bits are appended to the PHY layer header and the MAC layer header to generate a bit vector (S420). The bit vector is divided into at least two data blocks, wherein a first data block includes at least the CP mode bits (S430). A predefined number of tail bits are appended to each data block (S440). The two data blocks are mapped into at least two symbols, wherein the first data block is mapped to a first symbol, such that the first symbol is a first header symbol being transmitted (S450).