PLCSP MEMS Packaging Structure for Size and Cost Reduction
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Solution Overview
Problem
Conventional MEMS and IC devices face challenges in reducing size, increasing computational power, and decreasing cost, with existing fabrication techniques being inadequate for complex microsystems.
Innovation Solution
The development of a Package Level Chip Scale Package (PLCSP) method and structure for MEMS devices, which involves a MEMS chip with a CMOS substrate and a cap forming an enclosed cavity, bonded to a packaging substrate, eliminating wire bonding and mold compound encapsulation to achieve a compact and cost-effective packaging solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods (wire bonding and mold compound encapsulation) are used, then device reliability is maintained, but device size increases and manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the wire bonding and mold compound encapsulation steps from the conventional packaging process. By directly bonding the MEMS chip to the substrate without these intermediate components, the package size is reduced while maintaining device reliability through direct electrical and mechanical connections.
Solution Approach 2:
The patent merges the MEMS chip and substrate into a directly bonded integrated structure. The bonding regions on both the MEMS chip and substrate are brought into direct contact, combining multiple functions (electrical connection, mechanical support, thermal management) into a single integrated package without separate wire bonding and encapsulation layers.
2Ease of manufacture
If conventional packaging methods are used, then device reliability is maintained, but manufacturing cost increases
Solution Approach 1:
The patent removes the mold compound encapsulation step from the manufacturing process. By eliminating this material and its associated deposition and curing processes, manufacturing cost is reduced while reliability is maintained through the direct bonding structure that provides adequate protection without requiring additional encapsulation layers.
3Object-affected harmful factors
If traditional packaging structures are used, then thermal expansion mismatches occur, but structural simplicity is maintained
Solution Approach 1:
The patent extracts the mold compound layer that causes thermal expansion mismatches. By removing this intermediate material with different thermal properties, the direct bonding between MEMS chip and substrate eliminates thermal expansion interface issues, reducing harmful thermal stresses without adding structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller form factor and lower packaging costs compared to traditional methods, reducing external stresses and thermal expansion mismatches, while enabling the integration of various sensors like accelerometers and gyroscopes in compact MEMS packages.
Implementation Method 1
the cap and the first portion of the top surface form an enclosed cavity, wherein at least a MEMS device is formed on the first portion of the top substrate and disposed within the enclosed cavity
Implementation Method 2
bonding the first bonding region to the second bonding region
Data Source
AI summary
A method and structure for a PLCSP (Package Level Chip Scale Package) MEMS package. The method includes providing a MEMS chip having a CMOS substrate and a MEMS cap housing at least a MEMS device disposed upon the CMOS substrate. The MEMS chip is flipped and oriented on a packaging substrate such that the MEMS cap is disposed above a thinner region of the packaging substrate and the CMOS substrate is bonding to the packaging substrate at a thicker region, wherein bonding regions on each of the substrates are coupled. The device is sawed to form a package-level chip scale MEMS package.


