PLD Bus Interface Unit Emulating Different Processor Instruction Sets

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Solution Overview

Problem

Existing Programmable Logic Devices (PLDs) lack the ability to efficiently emulate a target processor with a different instruction set and bus interface protocol using available hard or soft processor cores, as they are either inflexible or resource-intensive to modify.

Innovation Solution

Implementing a bus interface unit within the PLD using programmable logic resources to translate bus transactions and an emulation program that converts instructions from the existing processor's set to the target processor's set, allowing a dedicated or soft processor to emulate a target processor with different protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a soft processor core is modified to conform to desired specifications, then adaptability to different instruction sets and bus protocols is improved, but area consumption increases and speed decreases

Engineering Contradiction:

Improveadaptability to different instruction sets and bus protocolsVSAvoidarea consumption

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The system is divided into two independent components: a fixed hard processor core and a separate bus interface unit. The processor core maintains its original instruction set and bus protocol, while the bus interface unit handles protocol translation. This segmentation allows the processor to remain area-efficient while achieving adaptability through the configurable bus interface unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A bus interface unit is introduced as an intermediary between the hard processor core and the target bus system. This intermediary translates bus transactions from the processor's native protocol to the desired target protocol, enabling the processor to interface with different bus standards without modifying the processor core itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a soft processor core is modified to conform to desired specifications, then adaptability to different instruction sets and bus protocols is improved, but operating speed decreases

Engineering Contradiction:

Improveadaptability to different instruction sets and bus protocolsVSAvoidoperating speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The system separates the processor core functions from the bus interface functions. The hard processor core executes instructions at its native high speed without modification, while the bus interface unit handles protocol translation operations. This segmentation ensures that the critical instruction execution path maintains maximum speed while adaptability is achieved in the I/O path.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bus interface unit acts as an intermediary that handles all protocol translation operations, isolating the processor core from any speed-degrading modifications. The processor core operates at its full native speed, while the bus interface unit manages the adaptability requirements without impacting the processor's operating frequency.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Area of stationary object

If a hard processor core is used, then area efficiency and operating speed are improved, but flexibility to support different instruction sets and bus protocols deteriorates

Engineering Contradiction:

Improvearea efficiencyVSAvoidflexibility to support different instruction sets and bus protocols

Core Design Contradiction:

Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The bus interface unit is designed with multi-functionality to support multiple bus protocols and instruction sets. By making the bus interface universal rather than the processor core, the system achieves flexibility without sacrificing the area efficiency of the hard processor core. The bus interface unit can be configured to work with different protocols while the processor remains fixed and compact.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The bus interface unit serves as a universal intermediary that can adapt to different bus protocols and instruction sets. This allows the hard processor core to maintain its fixed, area-efficient design while the bus interface handles the variability requirements, enabling the same processor to interface with multiple different systems.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7480786B1Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols

Publication Date: 2009.01.20 XILINX INC

AI summary

Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction sets and conform to different bus interface protocols. A bus interface unit is coupled to an existing processor in a PLD. The bus interface unit is implemented using the programmable logic resources of the PLD, while the existing processor can be a dedicated processor or an existing “soft” processor. The bus interface unit acts as a peripheral device to translate bus transactions from the existing bus protocol (i.e., the bus protocol understood by the existing processor) to the target bus protocol. In addition, a stored emulation program emulates the target instruction set while executing instructions using the instruction set supported by the existing processor.