PLD Bypass Routing Bus for Signal Pass-Through in Low Power Mode
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in passing signals when in low power mode, as they become open circuits, preventing the propagation of signals needed to wake up processors, necessitating external alternate channels, which complicates signal routing and power management.
Innovation Solution
The implementation of a bypass routing bus within PLDs that circumnavigates the logic core, allowing signals to be routed directly between source and destination I/O banks even when the logic core is in low power mode, using bypass routes and signal generators to maintain signal propagation without entering the logic core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLD is placed in low power mode to reduce power consumption, then power consumption is reduced, but signal propagation capability is lost
Solution Approach 1:
The PLD is segmented into multiple operational domains: the logic core can be placed in low power mode while I/O banks remain in normal operating mode. This segmentation allows selective power management where critical signal routing functions are maintained in active I/O banks while non-critical logic core operations are powered down, resolving the contradiction between power reduction and signal propagation capability
Solution Approach 2:
A bypass routing bus acts as an intermediary structure that directly connects source and destination I/O banks, circumventing the logic core. This intermediary pathway enables signal propagation independent of the logic core's operational state, allowing the logic core to be in low power mode while signals still propagate through the PLD via the bypass routing bus
2Use of energy by moving object
If the PLD is placed in low power mode, then power consumption is reduced, but the device becomes an open circuit requiring external alternate channels
Solution Approach 1:
The bypass routing bus provides a universal signal pathway that serves multiple functions: it enables wake-up signals to pass through the PLD when the logic core is powered down, allows through-signaling between I/O banks, and maintains PLD functionality as an active circuit element even when the logic core is in low power mode. This multi-functionality eliminates the need for external alternate channels and reduces overall system complexity
3Adaptability or versatility
If signals are routed through the logic core, then full processing functionality is available, but power consumption increases when in low power mode
Solution Approach 1:
The system dynamically adapts signal routing based on operational requirements: when full processing functionality is needed, signals route through the logic core in normal operating mode; when power reduction is prioritized and simple signal transmission suffices, signals route through the bypass routing bus while the logic core operates in low power mode. This dynamic adaptability resolves the contradiction between functionality and power consumption
Data Source
AI summary
A programmable logic device can include a logic core in low power mode, a source input/output (I/O) bank including at least one source I/O pin, wherein the source I/O bank operates in normal operating mode, and a destination I/O bank including at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode. The programmable logic device also can include a bypass routing bus coupled to the source I/O bank and the destination I/O bank, wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.