Programmable Shift-Register Clocking for PLD Delay Fault Testing
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Solution Overview
Problem
Current methods for testing transition delay faults in integrated circuits are inefficient due to high-speed testing requirements, which increase costs and power consumption, and are not deterministic, making it difficult to identify faults effectively.
Innovation Solution
A circuit and method utilizing a programmable shift register and clock generator to produce high-speed clock signals for scan-based testing at the operating speed of programmable logic devices, allowing for dynamic selection of clock pulses to detect defects and reprogram the logic device post-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional low speed tests are used, then power consumption is reduced and testing is simpler, but transition delay faults are not detected
Solution Approach 1:
The patent uses periodic clock pulses with programmable width to test the circuit under test. By applying a sequence of clock pulses with varying widths, the system can detect transition delay faults without requiring continuous high-speed operation, thereby reducing power consumption while maintaining fault detection capability
Solution Approach 2:
The patent changes the parameter of clock pulse width dynamically using a programmable shift register. By varying the pulse width parameter, the system can optimize between detection sensitivity and power consumption, applying longer pulses only when necessary for fault detection
2Reliability
If at-speed tests are applied, then transition delay faults are detected, but tester cost increases due to high speed requirements
Solution Approach 1:
The patent implements self-service by using the device under test's own programmable logic resources to generate and control the test clock signals. The programmable shift register within the device itself creates the test pulses, eliminating the need for complex external high-speed test equipment
Solution Approach 2:
The patent makes the programmable logic device serve multiple functions: it acts as both the device under test and the test signal generator. The same programmable logic resources that implement the user's design are also used to generate test clock pulses, reducing external tester requirements
3Reliability
If at-speed tests are applied, then transition delay faults are detected, but current consumption increases causing device heating
Solution Approach 1:
The patent uses periodic clock pulses with programmable width to test the circuit under test. By applying a sequence of clock pulses with varying widths, the system can detect transition delay faults without requiring continuous high-speed operation, thereby reducing power consumption while maintaining fault detection capability
Solution Approach 2:
The patent applies partial action by using a limited number of clock pulses with specific widths rather than continuous high-speed operation. The programmable shift register enables selective application of pulse sequences that are sufficient for fault detection without excessive power consumption
4Reliability
If BIST circuitry is used, then at-speed testing is achieved, but silicon area increases and implementation becomes difficult
Solution Approach 1:
The patent makes the programmable logic device serve multiple functions: it acts as both the device under test and the test signal generator. The same programmable logic resources that implement the user's design are also used to generate test clock pulses, reducing external tester requirements
Solution Approach 2:
The patent uses the existing programmable logic structure to copy or replicate the functionality of a test signal generator without adding dedicated BIST hardware. The programmable shift register leverages the device's inherent logic resources to create test patterns
Data Source
AI summary
A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.