PLD Clock Path Delay Tuning for Hold Time Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices (PLDs) face synchronization issues due to excessive delays in data and clock signals, leading to 'double clocking' and 'zero clocking' conditions, which existing approaches often fail to address effectively, especially in congested designs.
Innovation Solution
A method and system for synchronizing data and clock signals in PLDs by identifying hold time violations and selectively adjusting delay periods of clock paths to correct hold time violations without affecting setup time violations, allowing for partial correction of hold time issues without impacting critical data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data signals are delayed by routing through slow interconnects and detours to correct hold time violations, then hold time synchronization is improved, but configuration preparation time greatly increases and setup time violations may worsen
Solution Approach 1:
The patent segments the timing correction problem into two independent parts: hold time correction and setup time correction. By separating these corrections and applying them independently rather than using a single all-or-nothing approach, the method can address hold time violations without necessarily worsening setup time constraints, thereby reducing overall configuration preparation time while maintaining synchronization precision.
Solution Approach 2:
The patent applies local quality by selectively adjusting delay elements only in clock paths where hold time violations occur, rather than uniformly delaying all data paths. This targeted approach corrects specific synchronization problems without unnecessarily increasing configuration preparation time for the entire device, allowing partial solutions for congested designs.
2Manufacturing precision
If delay elements are added to clock paths to correct hold time violations, then hold time synchronization is improved, but device complexity increases
Solution Approach 1:
The patent extracts the timing correction function into separate, independently controllable delay elements that can be selectively applied only to clock paths requiring hold time correction. This separation allows the system to add minimal necessary complexity only where needed, rather than increasing complexity across the entire clock distribution network.
Solution Approach 2:
The patent implements dynamic adjustability by providing independently controllable delay elements that can be selectively enabled or disabled based on the specific timing requirements of different clock paths. This dynamic approach allows the system to adapt to varying hold time needs without permanently increasing the complexity of the overall clock distribution architecture.
Data Source
AI summary
Techniques for synchronizing data signals and clock signals of a programmable logic device (PLD) are provided. In one example, a method includes preparing an initial configuration of the PLD identifying a plurality of data paths associated with the data signals and a plurality of clock paths associated with the clock signals. The method also includes identifying a hold time violation associated with at least one of the data paths, wherein at least one of the clock signals is used to synchronize the data path. The method further includes selectively adjusting a delay period of a delay element of at least one of the clock paths associated with the clock signal to attempt to correct the hold time violation without concurrently attempting to correct any setup time violation associated with the data path.