PLD Clock and Data Recovery Using Grey Code Oscillator Calibration
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Solution Overview
Problem
Programmable logic devices (PLDs) face limitations due to the need for dedicated deserializer blocks that consume significant area and resources, imposing timing constraints and reducing the scope of user designs that can be implemented, leading to degraded performance and increased design time.
Innovation Solution
Implementing clock and data recovery circuitry using configurable logic blocks within PLDs, employing a ring type oscillator for calibration to recover clock and data signals from serial data streams, thereby reducing resource consumption and enhancing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated deserializer blocks are used to recover serialized data, then data recovery functionality is achieved, but significant area and routing resources are consumed
Solution Approach 1:
The patent implements a universal deserializer block that can be configured to perform multiple functions including clock recovery, data recovery, and deserialization for different data rates and formats. This single configurable block replaces the need for multiple dedicated deserializer blocks, thereby reducing area consumption while maintaining comprehensive data recovery functionality across various application scenarios.
2Measurement precision
If phase locked loop or accurate clock is used to oversample the data stream, then data recovery accuracy is improved, but timing burden on routing and clock circuitry increases
Solution Approach 1:
The deserializer block incorporates self-calibration and self-adjustment mechanisms that automatically optimize the oversampling clock frequency and phase alignment based on the incoming data stream characteristics. This self-service capability eliminates the need for external accurate clock sources and complex timing control circuitry, reducing device complexity while maintaining high data recovery accuracy through adaptive optimization.
3Reliability
If dedicated deserializer blocks are implemented, then clock and data recovery is achieved, but routing resources are limited and design scope is reduced
Solution Approach 1:
The configurable deserializer block can be programmed to support multiple serialization rates, data widths, and protocol formats, enabling a single block to serve various design requirements. This universality frees up routing resources that would otherwise be dedicated to multiple specialized deserializer blocks, thereby expanding the scope of user designs that can be implemented in the PLD.
4Speed
If multiple dedicated deserializer blocks are used, then higher data rates are supported, but area consumption and resource usage increase
Solution Approach 1:
The deserializer block features dynamically reconfigurable parameters including oversampling ratio, clock frequency, and data width that can be adjusted based on the required data rate. This dynamic adaptability allows a single block to support higher data rates through optimized configuration rather than requiring additional dedicated blocks, thereby maintaining area efficiency while achieving high-speed data recovery.
Data Source
AI summary
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.