Co-Simulation Port Value Transfer via PLD Configuration Block
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Solution Overview
Problem
Existing co-simulation systems for electronic systems require excessive resources and complex logic paths due to large memory maps and interconnects, limiting the operating frequency of hardware emulations.
Innovation Solution
A co-simulation system utilizing a programmable logic device (PLD) with a communication block and control block, where the control block reconfigures the PLD's programmable logic and interconnect resources to implement a design block emulation, using a fixed configuration data and internal configuration access to reduce resource requirements and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large memory map is implemented using multiplexers and address decoding logic, then the interface capability to access input and output ports is improved, but the device complexity and resource requirements increase excessively
Solution Approach 1:
The patent extracts the address decoding logic from the traditional memory map implementation and replaces it with a direct register-mapped peripheral approach. Each port is assigned a register address, and the memory-mapped I/O controller directly accesses these registers without complex decoding logic, thereby reducing device complexity while maintaining interface capability.
Solution Approach 2:
The patent implements a universal register-mapped interface that can handle multiple ports through a standardized addressing scheme. Instead of dedicated decoding logic for each port, a single controller handles all port accesses using generic read/write operations to register addresses, making the system more versatile and less complex.
2Adaptability or versatility
If a large memory map with extensive address decoding logic is used, then port access capability is improved, but the operating frequency is limited due to long combinational logic paths
Solution Approach 1:
The patent removes the lengthy address decoding combinational logic paths by replacing them with direct register accesses. The memory-mapped I/O controller writes directly to port registers without traversing complex decoding logic, significantly reducing propagation delay and enabling higher operating frequencies.
Solution Approach 2:
The patent pre-assigns fixed register addresses to each port during system initialization or configuration. This preliminary assignment eliminates the need for runtime address decoding, allowing the system to operate at higher frequencies since the address-to-port mapping is already established and does not require complex combinational logic during operation.
3Measurement precision
If address decoding logic is tied to physical locations of input and output ports, then port identification is improved, but interconnect resources are excessively required
Solution Approach 1:
The patent implements a universal register-mapped interface where all ports are accessed through a standardized addressing mechanism. Instead of dedicated interconnect paths from address decoding logic to each port's physical location, a single memory-mapped I/O controller handles all accesses using generic read/write operations, significantly reducing interconnect resource requirements while maintaining precise port identification through register addresses.
Data Source
AI summary
Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.