PLD Component Mapping for Latency Reduction
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Solution Overview
Problem
Conventional approaches to mapping synthesized components to physical hardware components in programmable logic devices (PLDs) fail to consider whether alternative compatible components could provide superior performance, leading to suboptimal implementations.
Innovation Solution
The proposed solution involves mapping synthesized components to models associated with multiple types of hardware components, allowing for selective assignment to physical locations that improve performance metrics such as latency, rather than solely based on compatibility with specific component specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional mapping approaches assign synthesized components to any compatible physical hardware component, then mapping simplicity is maintained, but performance optimization is lost
Solution Approach 1:
The patent creates mapping models in advance that associate synthesized components with multiple types of physical hardware components. These pre-established models enable the mapping process to consider multiple compatible options simultaneously, allowing performance optimization without significantly increasing mapping complexity during implementation.
Solution Approach 2:
The patent changes the mapping approach from single-component assignment to multi-component modeling. By representing synthesized components as compatible with multiple physical hardware component types through mapping models, the system can evaluate different performance parameters and select optimal assignments while maintaining manageable process complexity.
2Reliability
If synthesized components are mapped to multiple types of hardware components, then performance optimization is enabled, but mapping complexity increases
Solution Approach 1:
The patent makes mapping models universal by designing them to associate synthesized components with multiple types of physical hardware components. This multi-functionality allows a single mapping model to represent compatibility with various hardware component types, enabling performance optimization across different component selections without proportionally increasing model complexity.
3Reliability
If conventional approaches map synthesized components without considering alternative components, then mapping speed is maintained, but performance metrics deteriorate
Solution Approach 1:
By pre-establishing mapping models that define compatibility between synthesized components and multiple physical hardware component types, the system prepares optimization options in advance. This preliminary action enables faster evaluation during mapping since compatibility information is already structured, reducing the time penalty for considering multiple alternatives.
Solution Approach 2:
The patent creates abstract mapping models that copy and represent the compatibility relationships between synthesized components and physical hardware components. These model copies enable efficient evaluation of multiple mapping options without requiring direct analysis of actual hardware specifications during the mapping process, thus reducing time consumption.
Data Source
AI summary
Various techniques are provided for efficiently mapping synthesized components to physical hardware components of a PLD. In one example, a method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The method also includes converting the operations to a plurality of synthesized components. The method also includes mapping a selected one of the synthesized components to a model associated with first and second types of hardware components of the PLD. The selected synthesized component is compatible with first and second specifications of the first and second types of hardware components, respectively. The method also includes assigning the selected synthesized component to a physical location of the PLD comprising either the first type of hardware component or the second type of hardware component to improve a performance metric of the PLD configured with the design. Additional devices, systems and methods are also provided.