Programmable Logic Device Configuration Control Module
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Solution Overview
Problem
Large capacity programmable logic devices requiring more than 32 Mbit of configuration information face usability issues due to incompatible memory interfaces, leading to complex circuit structures and increased board space requirements.
Innovation Solution
An apparatus comprising a control module with a JTAG interface and a storage module, compatible with conventional configuration interfaces, which receives configuration information and configures or updates the programmable logic device without needing multiple memories, using a triple modular redundancy voting circuit for reliability and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memories each having a storage capacity less than or equal to 32 Mbit are adopted to configure the FPGA, then the configuration capacity requirement is met, but the number of circuit components increases and the occupied area of the circuit board increases
Solution Approach 1:
The patent combines multiple memory chips (e.g., two 16 Mbit chips or four 8 Mbit chips) into a single logical configuration unit that interfaces with the FPGA as one entity. The control module manages the combined memory resources, presenting a unified interface to the FPGA while internally coordinating data from multiple physical memory chips, thereby reducing the number of independent circuit components.
Solution Approach 2:
The control module serves multiple functions: it manages multiple memory chips, performs data aggregation and coordination, handles configuration protocols, and interfaces with the FPGA. This multi-functional design eliminates the need for separate control circuits for each memory chip, reducing overall circuit complexity while maintaining the required configuration capacity.
2Quantity of substance
If multiple memories each having a storage capacity less than or equal to 32 Mbit are adopted to configure the FPGA, then the configuration capacity requirement is met, but the occupied area of the circuit board increases
Solution Approach 1:
Multiple memory chips are merged into a single logical unit with shared control signals and unified interfacing to the FPGA. This consolidation reduces the total board space required compared to having multiple independent memory modules, each with its own control circuitry and spacing requirements.
Solution Approach 2:
The patent implements a hierarchical memory structure where multiple smaller memory chips are nested within a unified memory management framework. The control module acts as the outer container that orchestrates the inner memory chips, allowing compact arrangement on the circuit board while maintaining access to the total combined storage capacity.
3Quantity of substance
If memories such as SPI Flash memory, BPI PROM, or Platform Flash XL memory are used to configure the large capacity FPGA, then the configuration capacity requirement is met, but the interface compatibility is poor and usability decreases
Solution Approach 1:
The control module serves as an intermediary between the standard JTAG configuration interface and the non-volatile memory storage medium. It translates between the JTAG protocol expected by the FPGA and the memory interface protocols (SPI, BPI, etc.), providing interface compatibility without requiring the FPGA to directly support multiple memory protocols. This mediator approach maintains ease of operation by preserving the standard JTAG interface while enabling access to large capacity non-volatile memory.
Data Source
AI summary
An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.