PLD Configuration Memory Loading Using Validation and Stop Bits
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Solution Overview
Problem
Existing programmable logic devices (PLDs) face issues with inadvertently loading invalid or corrupted configuration data due to power failures during the pre-programming process, leading to potential device malfunction or damage, and lack of user control over loading configuration data upon power-up.
Innovation Solution
A PLD design that includes a non-volatile memory with a validation bit and a stop bit, where configuration data is loaded only if both bits exhibit specific logic states, allowing control logic to determine whether to load data into configuration memory cells, thereby preventing accidental loading during power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single validation bit is used to indicate successful configuration data loading, then the device can detect whether configuration data has been loaded, but the device cannot distinguish between valid configuration data and invalid data resulting from power failures during pre-programming
Solution Approach 1:
The patent divides the single validation bit into two separate validation bits (first validation bit and second validation bit). Each bit serves a specific validation purpose: the first validation bit indicates whether configuration data has been loaded into non-volatile memory, while the second validation bit indicates whether the loading process completed successfully without power failure. This segmentation allows the system to distinguish between valid and invalid configuration data, resolving the contradiction between measurement precision and reliability.
2Productivity
If configuration data is automatically loaded into configuration memory when the PLD is powered up and the validation bit is high, then the device can quickly initialize, but users cannot prevent loading of configuration data when desired for particular applications
Solution Approach 1:
The patent segments the validation process into two distinct validation bits that work together to provide both automatic loading capability and user control. The first validation bit enables automatic loading when set to logic high, maintaining fast initialization. The second validation bit provides user control by requiring both bits to be high before loading occurs. This segmentation resolves the contradiction by allowing both automatic operation and user-controlled operation modes.
Solution Approach 2:
The patent implements preliminary action by setting the second validation bit during the configuration programming process to indicate successful completion. This preliminary setting of the second bit before power-up ensures that when the device powers up, the control logic can immediately determine whether loading should occur without requiring user intervention, thus maintaining fast initialization while providing user control capability.
3Adaptability or versatility
If the non-volatile memory is erased and loaded with configuration data, then the device can be reconfigured for different applications, but power failure during pre-programming may leave the validation bit in a false state indicating valid data
Solution Approach 1:
The patent applies preliminary action by setting the first validation bit to logic high during the configuration loading process into non-volatile memory, before the actual configuration data is fully written. This preliminary setting ensures that if a power failure occurs during the loading process, the validation bit will already be in the correct state (logic high indicating loading was attempted), and the second validation bit will prevent false validation. This resolves the contradiction between reconfigurability and data integrity.
Solution Approach 2:
The patent implements feedback through the two-validation-bit system that provides continuous status information about the configuration loading process. The first bit feedbacks whether loading has started, and the second bit feedbacks whether loading completed successfully. This feedback mechanism allows the system to detect power failures during pre-programming and prevent false validation, resolving the contradiction between reconfigurability and reliability.
Data Source
AI summary
Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.