PLD Real-Time Debugging via Partial Reconfiguration
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Solution Overview
Problem
Debugging programmable logic devices (PLDs) in real-time is challenging due to the need to reset the device when configuring a tap at an interconnect to isolate functional failures, which can cause the failure condition to reset, requiring designers to wait for the failure to reoccur.
Innovation Solution
Implementing partial reconfiguration to add a debug design that taps interconnects without disturbing the existing logic design, allowing real-time debugging without resetting the PLD, by using configuration random access memory (CRAM) cells to selectively configure a subset of CRAM cells for the debug design while maintaining the original logic design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a new configuration file is created with a tap at the interconnect to debug the design, then the designer can observe the state of the signal associated with the interconnect, but the PLD must be reset which causes the failure condition to reset and requires waiting for the failure to reoccur
Solution Approach 1:
The configuration file is segmented into multiple configuration spaces (first configuration space for logic design, second configuration space for debug design). This allows the debug design with tap logic to be configured independently without resetting the entire PLD, enabling continuous observation of failure conditions.
Solution Approach 2:
The patent introduces a new dimension of configuration organization by using multiple configuration spaces. The debug design operates in a separate configuration space from the logic design, allowing simultaneous operation and eliminating the need to reset the device when adding debug functionality.
2Adaptability or versatility
If the PLD is reset to configure a new design with the tap, then the configuration can be updated, but the failure condition is lost and the designer must wait for intermittent failures to recur
Solution Approach 1:
The configuration memory is segmented into multiple configuration spaces that can be independently activated. The logic design resides in one configuration space while the debug design with tap logic resides in another, allowing the failure condition to be preserved while enabling debug functionality.
Solution Approach 2:
The debug design is prepared in advance in a separate configuration space without disturbing the running logic design. This preliminary configuration allows the tap logic to be ready and waiting, so when activated, the failure condition is already captured and can be observed without interruption.
3Ease of operation
If the entire PLD is reconfigured to add debug functionality, then the tap logic can be implemented, but the existing logic design configuration is disturbed
Solution Approach 1:
The configuration file is divided into multiple configuration spaces, each independently manageable. The debug design is configured in a separate space from the logic design, allowing independent configuration and activation without affecting the other, thus simplifying configuration management despite the added functionality.
Solution Approach 2:
Instead of reconfiguring the entire PLD, only the necessary portion (the debug design in the second configuration space) is configured. This partial configuration approach adds debug functionality while leaving the logic design configuration undisturbed, reducing overall configuration complexity.
Data Source
AI summary
Techniques and mechanisms allow a device such as a programmable logic device (PLD) to support real-time debugging of a system. The PLD may be configured to include a debug design without disturbing the configuration of a base logic design in the PLD.