Tile-Based PLD Net Delay Estimation Using Precomputed Lookup Tables
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing programmable logic device (PLD) implementation tools face challenges in accurately and efficiently estimating timing delays, which is crucial for optimizing design implementation but is often computationally expensive and resource-intensive.
Innovation Solution
The method involves constructing delay tables for sample areas in PLDs, using these tables to estimate net delays by calculating base delay values and route descriptions, and accounting for pin delays and wire variants to provide accurate and rapid delay estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If worst-case timing delays are calculated using specified delay values for every individual component, then measurement precision is improved, but computing time and power consumption increase significantly
Solution Approach 1:
The patent pre-calculates and stores timing delay values for all possible source-load pin pairs in lookup tables before the actual routing process. This preliminary computation allows the router to quickly retrieve pre-computed delay values instead of calculating them in real-time, thereby maintaining high measurement precision while significantly reducing computing time during design implementation.
Solution Approach 2:
The patent creates simplified delay models that capture the essential timing characteristics of the PLD architecture without requiring detailed analysis of every individual component. These delay models are pre-computed and stored, allowing the system to use approximate but sufficiently accurate delay estimates that consume far less computational resources while maintaining acceptable precision for routing decisions.
2Measurement precision
If detailed delay calculations are performed for every net, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent performs delay calculations in advance and stores the results in lookup tables. During the actual routing process, the system simply retrieves pre-computed delay values rather than performing intensive calculations, thereby maintaining accurate delay estimation while dramatically reducing power consumption during design tool operation.
Solution Approach 2:
The patent uses simplified delay models and pre-computed lookup tables that provide sufficiently accurate delay estimates without requiring expensive real-time calculations. These pre-computed structures serve as low-cost approximations that consume minimal power during routing operations while maintaining acceptable accuracy for practical design implementation.
3Reliability
If accurate delay estimation methods are used, then design implementation quality is improved, but computational resources required increase
Solution Approach 1:
The patent pre-computes delay values for all possible source-load pin combinations and stores them in lookup tables before the routing process begins. This approach maintains high design implementation quality by providing accurate delay information, while reducing computational resource requirements during actual routing by replacing complex real-time calculations with simple table lookups.
Solution Approach 2:
The patent divides the delay estimation problem into two distinct phases: an offline pre-computation phase where detailed delay analysis is performed and stored, and an online routing phase where pre-computed values are retrieved. This segmentation allows the system to maintain high implementation quality through thorough pre-computation while using minimal computational resources during the actual design implementation process.
Data Source
AI summary
Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.