Graphical Block-Based Design Exploration Tool for PLD Floor Planning
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Solution Overview
Problem
The complexity of programmable logic device (PLD) designs makes it difficult for designers to visualize and manage large or complex designs effectively, as existing tools often require navigating multiple detailed views and tables, which can be time-consuming and inefficient, especially in team-based development and incremental compilation processes.
Innovation Solution
A graphical block-based design exploration tool that displays multiple views (logical, physical, hierarchy, and timing) side-by-side or sequentially, with animation, allowing users to configure entity sizes, connections, and bundle states, facilitating quick understanding and manipulation of design structures, partitioning, and floor planning without the need for extensive recompilation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If designers use traditional detailed views and tables to manage PLD designs, then design accuracy is maintained, but design time and operational complexity increase significantly
Solution Approach 1:
The design is segmented into hierarchical levels (module level, block level, signal level) that can be independently displayed and manipulated. The graphical interface divides the complex design into manageable segments represented as blocks with visual connections, allowing designers to navigate and modify specific portions without reviewing the entire design detail level.
Solution Approach 2:
The patent introduces a graphical spatial dimension to represent logical connections between design elements. Instead of navigating through hierarchical text-based tables, the design is visualized as a two-dimensional graphical representation where blocks and signals are positioned spatially to reflect their logical relationships, enabling intuitive understanding and manipulation.
2Reliability
If multiple detailed views are provided for comprehensive design control, then design completeness is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The graphical block-based interface serves multiple functions simultaneously: it displays the design hierarchy, shows signal connections, enables partitioning operations, and provides floor planning capabilities all within a single unified view. This multi-functionality eliminates the need for separate detailed views for each function, reducing overall interface complexity while maintaining design completeness.
Solution Approach 2:
The graphical block representation acts as an intermediary between the detailed design data and the designer's needs. It translates complex hierarchical data into simplified visual blocks that can be easily manipulated, while still maintaining access to the underlying detailed information through context menus and property editors attached to each block.
3Manufacturing precision
If traditional design tools require extensive recompilation for design changes, then design accuracy is maintained, but productivity and development time worsen
Solution Approach 1:
The tool performs preliminary visualization and validation of design changes before final compilation. By displaying the graphical impact of proposed changes immediately, designers can verify accuracy and make adjustments without requiring repeated full compilations, thus maintaining design accuracy while improving development speed.
Data Source
AI summary
A graphical block-based design exploration tool displays multiple views of a chip design. These views may include a logical view, physical view, hierarchy view, and a timing display view, displayed side-by-side or sequentially with or without animation. Various entities and their relationships to each other are displayed in these different view arrangements to allow a user to quickly grasp the entire design and to perform design techniques such as partitioning and floor planning. The display properties are user configurable to organize the information based on user preferences.