PLD Initialization via DMA Buffering and Pacing Logic
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Solution Overview
Problem
Current methods for initializing programmable logic devices (PLDs) are inefficient, particularly in systems requiring frequent reprogramming, as they often rely on direct active control by a processor or serial EEPROMs, leading to prolonged system initialization times and increased costs due to processor bandwidth consumption and component limitations.
Innovation Solution
The use of direct memory access (DMA) to initialize PLDs, allowing PLD programming data to be transmitted at a DMA speed while the processor performs other tasks, thereby reducing system initialization time and eliminating the need for dedicated serial EEPROMs by using non-volatile memory external to the PLD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If active serial programming is used to initialize PLD, then program isolation and matching accuracy are improved, but programming speed deteriorates
Solution Approach 1:
The patent introduces a parallel loading interface as an intermediary between the serial EEPROM and PLD. This interface receives programming data in parallel from the EEPROM and converts it to the appropriate format for the PLD, enabling faster initialization while maintaining program isolation through the dedicated interface logic.
Solution Approach 2:
The patent transitions from serial data transmission to parallel data transmission by implementing a parallel loading interface. This dimensional change in data bus architecture allows multiple bits to be transferred simultaneously, dramatically increasing programming speed while the interface logic maintains the one-to-one program-PLD matching capability.
2Adaptability or versatility
If processor actively controls PLD programming, then programming flexibility is improved, but processor bandwidth consumption and initialization time worsen
Solution Approach 1:
The patent implements a self-service programming mechanism where the PLD automatically loads its configuration from the serial EEPROM through the parallel loading interface without requiring continuous processor intervention. The PLD's internal logic handles the programming sequence, freeing the processor to perform other initialization tasks simultaneously.
Solution Approach 2:
The patent prepares the programming data in advance by storing it in the serial EEPROM during system setup. The parallel loading interface is pre-configured to receive and process this data, allowing the PLD to be initialized quickly when needed without requiring the processor to generate or manage the programming data in real-time.
3Adaptability or versatility
If serial EEPROM is used for PLD programming, then field reprogramming capability is improved, but system cost and component complexity worsen
Solution Approach 1:
The patent makes the serial EEPROM serve multiple functions: it stores both the PLD programming data and other system configuration data. The parallel loading interface is designed to work with standard serial EEPROM components, allowing the same memory device to support both PLD initialization and general-purpose data storage, thereby reducing overall system component count.
4Device complexity
If low bit rate serial programming is used, then hardware simplicity is improved, but programming speed and system responsiveness deteriorate
Solution Approach 1:
The patent changes the data transmission dimension from serial (one bit at a time) to parallel (multiple bits simultaneously) through the parallel loading interface. This allows the system to maintain simple hardware connections while achieving high-speed data transfer by transmitting multiple programming bits in parallel from the serial EEPROM to the PLD.
Data Source
AI summary
An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.