Programmable Logic DSP Block With Integrated Floating-Point Arithmetic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing programmable logic devices (PLDs) lack efficient floating point operation capabilities, relying on programmable logic for at least a portion of floating point operations, which limits their performance in complex applications.
Innovation Solution
Incorporating specialized processing blocks with fundamental processing units that combine the functionality of multiple multipliers and adders, enabling single-step summation of multiplication products and reducing area requirements, along with integrated floating point circuitry for rounding and normalization, allowing for efficient floating point operations within the block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional discrete multipliers and adders are used in specialized processing blocks, then floating point operations can be performed, but the area required is large and efficiency is reduced
Solution Approach 1:
The patent combines multiple discrete multipliers and adders into an integrated fundamental processing unit. This unit performs multiple multiplication operations and sums the partial products in a single step, eliminating the need for separate adder circuits between multipliers. The merging of these functions into one compact unit reduces the overall area while maintaining floating point operation capability.
Solution Approach 2:
The fundamental processing unit is designed to perform multiple functions: it can execute several multiplication operations simultaneously, sum the partial products, and support floating point operations. This multi-functional design allows the same circuitry to handle various computational tasks that would traditionally require separate dedicated circuits, thereby reducing area while improving efficiency.
2Adaptability or versatility
If multiple discrete multipliers are used to perform multiplication operations, then computational capability is provided, but the area and complexity of the processing block increases
Solution Approach 1:
The patent merges multiple multiplier units and the summation logic into a single fundamental processing unit. Instead of having separate multipliers followed by separate adders to combine their outputs, the integrated unit performs all multiplication and summation operations internally in one step, simplifying the overall structure while maintaining the ability to perform multiple multiplication operations.
Solution Approach 2:
The fundamental processing unit is segmented into functional components that handle different aspects of the computation (multiplication stages, partial product generation, summation logic), but these segments are tightly integrated and operate cooperatively within a single unit. This segmentation allows for efficient resource utilization and reduced complexity compared to fully discrete implementations.
3Ease of operation
If floating point operations are implemented using only programmable logic, then flexibility is maintained, but operation speed and efficiency are limited
Solution Approach 1:
The patent integrates floating point operation circuitry directly into the fundamental processing unit, combining the arithmetic computation resources with the floating point control logic. This integration allows floating point operations to be performed using the same high-speed arithmetic units that perform integer operations, eliminating the speed limitations associated with purely programmable logic implementations while maintaining flexibility through programmable control.
Data Source
AI summary
A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.