PLD In-System Programmability Register Data Preservation
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Solution Overview
Problem
Current programmable logic devices (PLDs) with real-time in-system programmability (ISP) lack a method to retain register data during SRAM downloads, leading to system interruptions or unavailability.
Innovation Solution
A programmable logic device with a flash memory region for storing output pin states, a real-time ISP detection block, and a controller that clamps output pins to maintain register data, allowing seamless updates without power resets or interruptions by capturing and reloading register data using user flash memory or input pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If real-time in-system programmability is implemented in PLD, then field upgrades and development time are accelerated, but register data is lost and system operation is interrupted
Solution Approach 1:
The patent applies preliminary action by capturing and storing the current state of output pins in a look-up table memory before the SRAM download process begins. This pre-capture of register data ensures that when the configuration is updated, the original register values are already preserved and can be restored immediately after the update, thus preventing data loss and maintaining system continuity throughout the reconfiguration process.
2Adaptability or versatility
If SRAM download process is initiated after real-time ISP clears registers, then new configuration is loaded, but all previously stored register values are lost and I/O pins are tri-stated
Solution Approach 1:
The patent applies preliminary action by capturing and storing the current state of output pins in a look-up table memory before the SRAM download process begins. This pre-capture of register data ensures that when the configuration is updated, the original register values are already preserved and can be restored immediately after the update, thus preventing data loss and maintaining system continuity throughout the reconfiguration process.
Solution Approach 2:
The patent applies copying by creating a duplicate copy of the register data stored in the look-up table memory. This copy serves as a backup that can be restored after the SRAM download, effectively preserving the original information while allowing the configuration to be updated. The copying mechanism ensures that no register data is permanently lost during the reconfiguration process.
3Adaptability or versatility
If power cycle is used to force flash to SRAM download, then configuration is updated, but system operation is interrupted
Solution Approach 1:
The patent applies preliminary action by capturing and storing the current state of output pins in a look-up table memory before the SRAM download process begins. This pre-capture of register data ensures that when the configuration is updated, the original register values are already preserved and can be restored immediately after the update, thus preventing data loss and maintaining system continuity throughout the reconfiguration process.
Solution Approach 2:
The patent applies continuity of useful action by ensuring that the system remains operational throughout the configuration update process. By capturing register data beforehand and restoring it after the SRAM download without requiring a power cycle, the system maintains continuous operation. The I/O pins remain active and the logic blocks continue to function, eliminating system downtime and maintaining uninterrupted service.
Data Source
AI summary
A PLD having real-time in-system programmability (ISP) capability is provided. The PLD includes a configuration memory region into which the updated configuration is obtained. A user memory region stores the state for registers of the PLD. The configuration memory region communicates the updated configuration to a core logic region that includes a real-time ISP detection block that detects the initiation of a real-time ISP operation. A controller is in communication with the logic block. The PLD maintains register data by reading a state of the registers of the PLD/logic block and clamping the output pins before the core logic region is being updated. The state of the registers is saved in the memory region as directed by the controller. Upon completion of the update into the logic array, the registers of the PLD are cleared and a control signal from a memory interface triggers the controller to read stored the register data back from the memory and reload the registers. Upon the completion of reloading the registers, the output pins are released for normal device operation.