Merging Incrementer and Multiplier Logic in PLDs
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Solution Overview
Problem
Conventional methods for synthesizing and mapping incrementer-multiplier operations in programmable logic devices (PLDs) result in significant propagation delays and inefficient resource allocation, particularly for large numerical inputs, leading to increased clock periods and reduced clock frequencies.
Innovation Solution
A methodology is introduced to merge the arithmetic operations of incrementer-multiplier operations into efficient parallelized implementations by decomposing them into constituent operations such as addition and shift operations, allowing for the embedding of the incrementer operation within partial products, thereby reducing resource consumption and propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional synthesis methods are used for incrementer-multiplier operations, then implementation is straightforward, but propagation delay increases and clock frequency decreases
Solution Approach 1:
The incrementer-multiplier operation is segmented into distinct phases: incrementer phase, multiplier phase, and output phase. Each phase is implemented using separate configurable logic blocks, allowing independent optimization of each segment and reducing overall propagation delay through parallel processing paths.
Solution Approach 2:
The patent implements dynamic operation modes that can be selected based on input characteristics. For large numerical inputs, an optimized path is selected that reduces propagation delay, while for smaller inputs, a different path is used. This dynamic adaptation allows the system to maintain low delay across varying input conditions.
2Productivity
If conventional synthesis methods are used for incrementer-multiplier operations, then resource allocation is simple, but configurable resources and interconnections are inefficiently allocated
Solution Approach 1:
The patent creates a universal incrementer-multiplier core that can handle various input sizes and operation types using the same configurable logic blocks. The same hardware resources can be reconfigured to implement different incrementer-multiplier operations, maximizing resource utilization efficiency across diverse applications.
Solution Approach 2:
The synthesis methodology uses parameter changes to optimize resource allocation based on input bit-width and operation requirements. Configuration parameters such as incrementer size, multiplier size, and operation mode are adjusted to match the specific application, allowing efficient use of configurable resources without over-provisioning.
3Productivity
If conventional synthesis methods are used, then design implementation is straightforward, but clock period increases and computational performance decreases
Solution Approach 1:
The patent performs preliminary analysis of the incrementer-multiplier operation parameters during synthesis to determine the optimal implementation path before actual implementation. Configuration data is pre-calculated based on input bit-width and operation type, allowing the hardware to execute the operation at maximum speed without runtime decision-making overhead.
Solution Approach 2:
The incrementer operation is nested within the multiplier operation structure, where the incrementer output directly feeds into the multiplier input without requiring separate output registration. This nesting eliminates intermediate delays and allows the operations to be tightly coupled, improving overall computational performance.
Data Source
AI summary
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The computer-implemented method also includes synthesizing the design into a plurality of PLD components. In the computer-implemented method, the synthesizing includes detecting an incrementer-multiplier operation in the design and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.