PLD I/O Cell Configuration Using Separate Boundary Scan Shift Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable logic devices (PLDs) face issues with configuration data repeatability and routing congestion due to a single data shift register (DSR) serving both programmable logic blocks and I/O rings, leading to unnecessary delays and increased memory requirements.
Innovation Solution
Modifying boundary scan cells to form a separate I/O ring configuration data shift register, allowing configuration data to bypass the core DSR and directly configure I/O cells through a JTAG controller, thereby preventing phantom bits and reducing routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single configuration data shift register (DSR) is used to configure both programmable logic blocks and I/O cells, then device complexity is reduced, but configuration delays increase due to phantom bits and routing congestion occurs
Solution Approach 1:
The patent divides the configuration system into two separate DSRs: one dedicated to programmable logic blocks and another dedicated to I/O cells. This segmentation eliminates the phantom bit problem where unused bits cause delays, as each DSR is sized precisely for its intended purpose. The routing congestion is also reduced by separating the configuration paths for core logic and I/O cells.
2Device complexity
If a single DSR is used for both core and I/O ring configuration, then device complexity is reduced, but configuration data repeatability deteriorates requiring larger external memory
Solution Approach 1:
By segmenting the configuration system into separate DSRs for core logic and I/O cells, the patent enables independent configuration sequences. This separation improves data repeatability because each DSR can be independently programmed and reset, allowing external memory to exploit redundancy more effectively. The configuration data for each segment can be optimized separately for repeatability.
3Productivity
If a separate I/O ring DSR is implemented, then configuration efficiency improves by eliminating phantom bits, but die complexity and cost increase
Solution Approach 1:
The patent utilizes existing boundary scan cells, which are standard components in FPGAs for testing purposes, and repurposes them to form the I/O ring configuration DSR. This self-service approach allows the device to configure I/O cells without requiring entirely new dedicated infrastructure, thereby improving configuration efficiency while minimizing the increase in die complexity. The boundary scan cells are already present in the device architecture.
Data Source
AI summary
A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the plurality of programmable logic blocks; a plurality of input/output (I/O cells), each I/O cell associating with a corresponding set of I/O configuration memory cells; and a plurality of boundary scan cells corresponding to the plurality of I/O cells, each boundary scan being configurable to form a second data shift register for the I/O configuration memory cells.