PLD I/O Bus Protection Circuit for Power-On Voltage Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in protecting their input/output (I/O) buses from varying supply voltages during power-on sequences, which can lead to reliability issues and reduced operational lifespan.
Innovation Solution
The implementation of a bus protection control signal generator and a cascode transistor arrangement within the PLD provides I/O bus supply voltage protection by biasing protection transistors with bus protection control signals, ensuring transistor voltages remain within safe operational limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If I/O buses are exposed to varying supply voltages during power-on sequences, then the PLD can operate with a wide range of bus supply voltages (1.2v to 3.3v), but the I/O transistors may be damaged by voltages exceeding their tolerance (1.8v +/-10%)
Solution Approach 1:
The patent introduces protection transistors (first and second protection transistors) as intermediary elements between the I/O bus and the core I/O transistors. These protection transistors act as voltage mediators that limit the maximum voltage passing through to the sensitive I/O transistors, allowing the system to accept higher bus voltages (up to 3.3v) while protecting the internal transistors from damage.
Solution Approach 2:
The protection transistors are configured to automatically activate when bus supply voltage exceeds safe levels, performing preliminary protection before damage can occur. The circuit structure ensures that voltage limiting is in place before the I/O transistors are exposed to harmful voltages during power-on sequences.
2Reliability
If protection circuits are added to I/O buses, then transistor voltage protection is improved, but device complexity increases
Solution Approach 1:
The protection functionality is merged with the existing I/O bus structure by integrating protection transistors directly into the I/O circuit path. The first protection transistor is combined with the pull-up resistor, and the second protection transistor is combined with the pull-down resistor, creating a unified circuit that provides both I/O functionality and voltage protection without requiring completely separate protection circuits.
Solution Approach 2:
The protection transistor circuit serves multiple functions simultaneously: it acts as a voltage limiter to protect I/O transistors, provides pull-up and pull-down functionality through integrated resistors, and enables the I/O bus to operate with various supply voltages. This multi-functionality reduces the need for additional dedicated protection components.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.