PLD I/O Block Delay for Hold Time Correction
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Solution Overview
Problem
In programmable logic devices, pre-routing timing estimates are often inaccurate due to unknown signal paths, leading to significant processing time and resource requirements for correcting timing errors detected after routing.
Innovation Solution
The implementation of delay circuitry in input/output blocks allows for selective delay of input signals to correct hold time errors without altering configured logic blocks or routing resources, thereby avoiding the need to repeat synthesis, mapping, and placement operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If pre-routing timing analysis is performed, then timing compliance can be checked early, but the timing estimates are inaccurate due to unknown signal paths
Solution Approach 1:
The patent applies preliminary action by performing timing analysis before final routing is completed. The system estimates signal path delays using available routing information and performs timing checks early in the design process, allowing potential timing violations to be detected and corrected before final implementation, thus saving time despite the approximate nature of pre-routing estimates
2Reliability
If timing errors are corrected by repeating mapping, placement, and routing operations, then timing compliance can be achieved, but significant processing time and resources are required
Solution Approach 1:
The patent extracts the timing correction function from the complex iterative mapping-placement-routing process. By identifying specific timing violations and applying targeted corrections only to affected signal paths, the system avoids repeating entire design cycles. This extraction approach maintains timing compliance while dramatically reducing the processing time and resources required compared to full re-synthesis and re-routing
Solution Approach 2:
The patent applies partial action by performing timing analysis and correction on only those signal paths that exhibit timing violations, rather than re-processing the entire design. The system identifies specific critical paths and applies corrections selectively, avoiding the excessive processing that would result from repeating all mapping, placement, and routing operations
3Manufacturing precision
If delay circuitry is added to correct hold time errors, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by inserting delay circuitry only at specific locations where timing violations occur, rather than adding delay elements throughout the entire device. The system identifies critical signal paths with hold time violations and applies localized corrections using I/O block delay capabilities, thereby improving timing precision without significantly increasing overall device complexity
Data Source
AI summary
Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.