PLD Logic Element Redundancy for Lower-Area Defect Repair
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Solution Overview
Problem
Current Programmable Logic Devices (PLDs) with redundancy schemes face challenges due to the row granularity of one Logic Array Block, leading to significant space penalties and interconnect issues, including increased costs and propagation delays.
Innovation Solution
Implementing redundancy at the logic element level within each row, using staggered inter-LAB lines and additional programmable connections to enable each logic element to be replaced by a non-defective one, reducing the need for extra routing switches and allowing for more efficient use of chip space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row-based redundancy scheme with LAB granularity is used, then production yields are improved by providing redundant circuitry, but chip space is significantly reduced due to the overhead of redundant logic rows
Solution Approach 1:
The patent segments the redundancy mechanism from the traditional row-based LAB level to the logic element level within each LAB. Instead of dedicating entire rows of logic elements as redundant, the invention allows individual logic elements to be marked as redundant and replaced independently. This segmentation enables much finer control over the redundancy overhead, reducing the space penalty from potentially entire rows to just individual logic element instances.
Solution Approach 2:
The patent applies local quality by allowing different logic elements within the same LAB to have different redundancy statuses. Some logic elements can be marked as redundant while others remain functional, enabling selective redundancy application based on local defect patterns rather than applying blanket redundancy across entire rows or blocks.
2Reliability
If row-based redundancy with LAB granularity is used, then defective rows can be bypassed and replaced, but interconnect complexity increases due to the need for extra routing switches and extended inter-LAB lines
Solution Approach 1:
The patent segments the redundancy control to the individual logic element level rather than row level. Each logic element can independently utilize redundant instances through local multiplexer control, eliminating the need for complex row-level routing switches and extended inter-LAB lines that would be required for traditional row-based redundancy schemes.
Solution Approach 2:
The patent introduces local multiplexers within each LAB as intermediary elements that enable logic element replacement. These multiplexers act as mediators between the functional logic elements and their redundant counterparts, allowing seamless switching without requiring complex external routing infrastructure.
3Area of stationary object
If logic element level redundancy is implemented, then the overhead of redundant logic is reduced and more chip space is available, but the complexity of managing individual logic element replacement increases
Solution Approach 1:
The patent implements self-service through automatic defect detection and replacement mechanisms. The system automatically identifies defective logic elements and activates their redundant counterparts without requiring complex manual management or complex control logic. The redundancy management is simplified through programmable markers that automatically configure the replacement behavior.
Data Source
AI summary
A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element.