PLD Low-Power Entry With Deterministic Internal State Control

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Solution Overview

Problem

Existing programmable logic integrated circuits (PLDs) lack the ability to deterministically place their internal logic into a specified state before entering low-power mode, leading to unpredictable resume configurations and requiring additional external control logic, which complicates system design.

Innovation Solution

Incorporating a low-power mode control circuit within the PLD that allows for user-specified control of the low-power mode entry sequence, enabling the PLD to manage its internal state and clocks deterministically using a single low-power enable input, ensuring consistent operation upon resuming from low-power mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a low-power mode enable input is added to the PLD, then the PLD can enter low-power mode to reduce power consumption, but the PLD cannot deterministically place its internal logic into a specified state before entering low-power mode

Engineering Contradiction:

Improvepower consumptionVSAvoiddeterministic state placement

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent implements preliminary actions by providing a programmable entry sequence that executes specific operations before the PLD transitions to low-power mode. This sequence can deterministically place internal logic into specified states, configure memory elements, and prepare the device for low-power operation while maintaining reliability upon resume.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces dynamic control through a programmable entry sequence that can be customized based on the specific application requirements. The sequence allows flexible configuration of internal logic states and control elements, enabling the PLD to adaptively manage its transition to and from low-power mode while ensuring deterministic behavior.

Inventive Principle:

Principle #15Dynamics

2Reliability

If additional external control logic is used to manage low-power mode entry, then the PLD can achieve deterministic state placement, but the system design becomes more complex

Engineering Contradiction:

Improvedeterministic state placementVSAvoidsystem design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the low-power mode control functionality directly into the PLD by integrating a control element and programmable entry sequence within the device. This consolidation eliminates the need for separate external control logic, reducing system design complexity while maintaining deterministic state placement capability through the programmable sequence.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent enables the PLD to self-manage its low-power mode transition by providing an internal programmable entry sequence that autonomously configures internal logic and control elements. The device performs its own state management without requiring external control logic, simplifying the overall system design while ensuring reliable deterministic behavior.

Inventive Principle:

Principle #25Self-service

3Loss of energy

If the PLD enters low-power mode without deterministic state placement, then power consumption is reduced, but the resume configuration becomes unpredictable

Engineering Contradiction:

Improvepower consumptionVSAvoidresume configuration predictability

Core Design Contradiction:

Loss of energyVSEase of operation

Solution Approach 1:

The patent executes preliminary actions through a programmable entry sequence that deterministically configures internal logic states and control elements before transitioning to low-power mode. This ensures that when the PLD resumes operation, the configuration is predictable and reliable, eliminating the unpredictability associated with non-deterministic state placement.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7886261B1Programmable logic device adapted to enter a low-power mode

Publication Date: 2011.02.08 MICROSEMI SOC CORP

AI summary

A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.